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    IC UC66 Search Results

    IC UC66 Result Highlights (5)

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    7UL1G07FU
    PCB Symbol, Footprint & 3D Model
    		 Toshiba Electronic Devices & Storage Corporation One-Gate Logic(L-MOS), Non-Inverter Buffer (Open Drain), SOT-353 (USV), -40 to 125 degC Visit Toshiba Electronic Devices & Storage Corporation
    74HC4053FT
    PCB Symbol, Footprint & 3D Model
    		 Toshiba Electronic Devices & Storage Corporation CMOS Logic IC, SPDT(1:2)/Analog Multiplexer, TSSOP16B, -40 to 125 degC Visit Toshiba Electronic Devices & Storage Corporation
    7UL2T125FK
    PCB Symbol, Footprint & 3D Model
    		 Toshiba Electronic Devices & Storage Corporation One-Gate Logic(L-MOS), Buffer with Level Shifting, SOT-765 (US8), 2 in 1, -40 to 125 degC Visit Toshiba Electronic Devices & Storage Corporation
    7UL2T126FK
    PCB Symbol, Footprint & 3D Model
    		 Toshiba Electronic Devices & Storage Corporation One-Gate Logic(L-MOS), Buffer with Level Shifting, SOT-765 (US8), 2 in 1, -40 to 125 degC Visit Toshiba Electronic Devices & Storage Corporation
    74HC4051FT
    PCB Symbol, Footprint & 3D Model
    		 Toshiba Electronic Devices & Storage Corporation CMOS Logic IC, SP8T(1:8)/Analog Multiplexer, TSSOP16B, -40 to 125 degC Visit Toshiba Electronic Devices & Storage Corporation

    IC UC66 Datasheets Context Search

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    ulc xc3030

    Abstract: ic UC66 CPLD EPM 7128 XC3030A-5PL84C
    Contextual Info: T em ic UC Series_ Matra MHS Universal Logic Circuits Description The UC series of ULC s is w ell suited for converting medium- to large-sized CPLDs and FPGAs. D evices are implemented in high-performance CMOS technology with 0.85-mm drawn channel lengths, and are capable


    OCR Scan     		85-mm 300-mil 150-mil ulc xc3030 ic UC66 CPLD EPM 7128 XC3030A-5PL84C PDF

    UD10

    Abstract: UD09 UD27 matra universal logic circuit
    Contextual Info: T e m ic UD Series Matra M H S Universal Logic Circuits Description The U D series of U L C ^ s is optimized for conversion of small- to medium-sized PLDs, CPLDs and FPGAs. This series use a unique architecture that provides a high I/O-to-gate ratio. Devices are implemented in


    OCR Scan     		PDF