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    IC-NQ P 60 Search Results

    IC-NQ P 60 Result Highlights (5)

    Part ECAD Model Manufacturer Description Download Buy
    74HC4053FT Toshiba Electronic Devices & Storage Corporation CMOS Logic IC, SPDT(1:2)/Analog Multiplexer, TSSOP16B, -40 to 125 degC Visit Toshiba Electronic Devices & Storage Corporation
    7UL2T125FK Toshiba Electronic Devices & Storage Corporation One-Gate Logic(L-MOS), Buffer, SOT-765 (US8), -40 to 85 degC Visit Toshiba Electronic Devices & Storage Corporation
    7UL2T126FK Toshiba Electronic Devices & Storage Corporation One-Gate Logic(L-MOS), Buffer, SOT-765 (US8), -40 to 85 degC Visit Toshiba Electronic Devices & Storage Corporation
    74HC4051FT Toshiba Electronic Devices & Storage Corporation CMOS Logic IC, SP8T(1:8)/Analog Multiplexer, TSSOP16B, -40 to 125 degC Visit Toshiba Electronic Devices & Storage Corporation
    7UL1G07FU Toshiba Electronic Devices & Storage Corporation One-Gate Logic(L-MOS), Non-Inverter Buffer (Open Drain), USV, -40 to 85 degC Visit Toshiba Electronic Devices & Storage Corporation

    IC-NQ P 60 Datasheets Context Search

    Catalog Datasheet MFG & Type PDF Document Tags

    TYP33

    Abstract: HC 193 n
    Text: 74HC/HCT75 MSI QUAD BISTABLE TRANSPARENT LATCH FEATURES • • • • Complementary Q and Q outputs V c c and GND on the centre pins Output capability: standard ICC category: MSI T Y P IC A L HC tP H L / iP L H propag ation delay n D to nQ , nQ L E n.n to nQ , nQ


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    PDF 74HC/HCT75 7Z93J51 TYP33 HC 193 n

    ci 4538

    Abstract: No abstract text available
    Text: 74HC/HCT4538 MSI DUAL RETRIGGERABLE PRECISION MONOSTABLE M ULTIVIBRATOR FEA TU R ES TY P IC A L SYMBOL • • Separate reset inputs Triggering from leading or trailing edge Output capability: standard lc c category: MSI tP H l/ 'P LH propagation delay nAQ, nA-j to nQ, nQ


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    PDF 74HC/HCT4538 74HC/HCT4538 ci 4538

    EF6809CM

    Abstract: EF6809CV TF-680 ST EF68B09 ef68b09 EF6800 E0RA How to processor of thai dtv EF6809J EF6809
    Text: HMOS 8 - B IT M IC R O P R O C E S S IN G U N IT The EF6809 is a re vo lu tio n är. . w h i c h rvupports m o d e m denco, Mg r> p e r ' o i m j n i . e prograrnm .nq 8-1" H IG H D E N S ITY N -C H A N N E L . S IL IC O N -G A T E t e c h n i / ] u O s m . cti


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    PDF EF6800 16-Bit STD-B83C F6809 MO-047-AC CB-521 PLCC44 CB-708 EF6809CM EF6809CV TF-680 ST EF68B09 ef68b09 E0RA How to processor of thai dtv EF6809J EF6809

    YTFA

    Abstract: No abstract text available
    Text: XFMRS DWN-: ~xj CHK.: ^ DATF : Sep—2 9 —04 # J Nq APP.: nATF. S e p - 2 9 - 0 4 DATF:5eP ~ 2 9 ~ 0 4 1XFSH1M SERIES SHIELDED INDUCTORS M e ch a n ic a l S e c h e m a tic : D im en sions: 1 o- 2 o- 1 5.38 13.97 - 7 .4 9 - Max x D rO o o o m Ol 10.16 I— 4.4 5


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    PDF Sep-29-04 5ep-29-04 0047SH1M 1XF0D1D05H1M 1XF0D1505H1M 1XF00220SH1M 1XF00330SH1M 470SH1M 1XF006805H1M 1XF010005H1M YTFA

    26AWGx2C

    Abstract: ml 94v-0 28AWGX1 45p PVC cable usb A A dwg R45P PVC 45P
    Text: REV. A B 1200+40 ECN. NQ APPI. HC000660 IC 0 0 2 0 5 6 P IN 1 a rm rïïïi He C UNNECTIDN STRATAC 9 12 11 4 10 SH ELL USB RED WHITE 1 2 3 GREEN ±SL 4 SH ELL NOTE i 1. SP EC I F I CATION! 1. 1 O PER A TIN G VDLTAGE ! 30 VAC 1 .2 O PER A TIN G CURRENT i 1AMP MAX


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    PDF HC000660 IC002056 500VDC 28AWGX1 26AWGX2C JB2010C-07 CQV12D04UB4-01 605-00Q0-646 ml 94v-0 45p PVC cable usb A A dwg R45P PVC 45P

    74HC-HCT221

    Abstract: z224
    Text: 74H C/H CT221 MSI S U P E R S E D E S D A T A O F A P R I L 1988 D U A L N O N - R E T R I G G E R A B L E M O N O S T A B L E M U L T I V I B R A T O R W IT H R E S E T FEATU RES • T Y P IC A L Pulse width variance is typically less SYM BO L PARAM ETER


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    PDF CT221 74HC-HCT221 z224

    74HCT logic family specifications 245

    Abstract: 74HC 74HCT HD10 LT 805
    Text: 74HC/HCT221 MSI S U P E R S E D E S D A T A O F A P R IL 1988 DUAL N O N-RETRIG GERABLE MONOSTABLE M U L T IV IB R A T O R W ITH RESET FEA TU RES • T Y P IC A L • Pulse width variance is typically less than ± 5% Pin-out identical to "1 23 " Overriding reset terminates output


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    PDF 74HC/HCT221 10Ki2 7Z22448 74HCT logic family specifications 245 74HC 74HCT HD10 LT 805

    R419157

    Abstract: R4118XX121 nato BNC 7044 R413810000
    Text: COAXIAL ATTENUATORS EUROPEAN MILITARY APPROVED PREFERRED PRODUCTS LIST MICROWAVE COMPONENTS : Förderverein Für Elektrotechnische Normung e.V. Ceneiec Electronic Components Committee Military Usage And Harmonisation Advisory Group f . I““ i _f _ V -/V « /


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    PDF R413810000 R413820000 R414420000 R414510000 R414706000 R419157 R4118XX121 nato BNC 7044

    Untitled

    Abstract: No abstract text available
    Text: 7 T H IS DRAW ING IS U N P U B L IS H E D . RE LEA S E D FOR 6 5 4 3 2 PU B LIC ATIO N LOC ALL INTERNATIONAL RIGHTS RESERVED. COPYRIGHT - AD BY TYCO ELECTRONICS CORPORATION. REVISIONS D IS T 47 LTR D E S C R IP T IO N AC • P O S IT IO N #1 REVISED PER ECO -08-009495


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    PDF

    Untitled

    Abstract: No abstract text available
    Text: 74HC/HCT423 MSI J \ _ DUAL RETRIGGERABLE MONOSTABLE MULTIVIBRATOR WITH RESET F E A TU R E S • • • • • TYPICAL DC triggered from active H IG H or active LOW inputs Retriggerable for very long pulses up to 100% duty factor Direct reset terminates output pulse


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    PDF 74HC/HCT423

    7Z93

    Abstract: HCT74 74HC-HCT74 74HC 74HCT
    Text: 7 4 H C /H C T 7 4 flip-flops D U A L D -TY PE F LIP-FLO P W IT H SET A N D RESET; P O S IT IV E -E D G E T R IG G E R FE A TU R ES T Y P IC A L • O utput capability: standard • 1.00 ca te g o ry : flip -flo p s SYMBOL T he 7 4 H C /H C T 7 4 are dual positiveedge triggered, D -type flip -flo p s w ith


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    PDF 74HC/HCT74 74HC/HCT74 7Z93 HCT74 74HC-HCT74 74HC 74HCT

    74HC-HCT221

    Abstract: HCT221
    Text: 74HC/HCT221 MSI 7 V. SUPERSEDES D A T A OF A P R IL 1988 DUAL NON-RETRIGG ERABLE MONOSTABLE M U LTIVIB R A TO R W ITH RESET FE A TU R E S • TYPICAL • Pulse width variance is typically less than ± 5% Pin-out identical to " 1 2 3 " Overriding reset terminates output


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    PDF 74HC/HCT221 74HC-HCT221 HCT221

    Untitled

    Abstract: No abstract text available
    Text: 74HC/HCT423 M SI D U A L R ET R IG G ER A BLE MONOSTABLE M U LT IV IBR A T O R WITH RESET FE A TU R ES • • * * * TYPICAL DC triggered fro m active H IG H o r active LOW inputs Retriggerable fo r very long pulses up to 100% d u ty fa cto r D ire ct reset term inates o u tp u t pulse


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    PDF 74HC/HCT423

    HCT74

    Abstract: lz93 100 pin 74HC 74HCT
    Text: 74H C /H C T 74 P H IL IP S IN T E R N A T IO N A L bSE D flip-flops IP H IN ^ v_ DUAL D-TYPE FLIP-FLOP WITH SET AND RESET; POSITIVE-EDGE TRIGGER FEATURES TYPIC AL • O utp u t capability: standard • Ic C cate9orV : flip-flops SYMBOL G E N E R A L D E S C R IP T IO N


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    PDF 74HC/HCT74 7110fleb HCT74 lz93 100 pin 74HC 74HCT

    6R190

    Abstract: HCT74 Flip-Flops D
    Text: 74HC/HCT74 flip-flops D U A L D-TYPE FLIP-FLOP WITH SET A N D RESET; PO SITIVE-EDGE T R IG G ER FEATURES T Y P IC A L • Output capability: standard • lc c category: flip-flops SYM BO L G E N E R A L D E S C R IP T IO N Schm itt-trigger action in the clock input


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    PDF 74HC/HCT74 6R190 HCT74 Flip-Flops D

    Untitled

    Abstract: No abstract text available
    Text: 74H C /H C T 42 3 MSI J V DUAL RETRIGGERABLE MONOSTABLE M ULTIVIBRATOR WITH RESET FEATU R ES * • * * • TYPICAL DC triggered fro m active H IG H or active LOW inputs Retriggerable fo r very long pulses up to 100% d u ty fa cto r D irect reset term inates o u tp u t pulse


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    PDF

    MAX232

    Abstract: No abstract text available
    Text: 74HC/HCT112 flip-flops DUAL JK FLIP-FLOP WITH SET AND RESET; NEGATIVE-EDGE TRIGGER FEATURES • • • TYPICAL Asynchronous set and reset Output capability: standard l£ £ category: flip-flops GENERAL DESCRIPTION ic p 1K JT u IT HCT 17 15 18 19 15 19 tP H l/


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    PDF 74HC/HCT112 MAX232

    74HC74

    Abstract: 74ls74 timing setup hold 74hc74 pin diagram 74LS74 PINOUT 74HC74 pin configuration 74hct74 Current 74HCT74 TTL 74hc74 74HC GD74HCT74
    Text: GD54/74HC74, GD54/74HCT74 DUAL D-TYPE FLIP-FLOPS WITH PRESET & CLEAR General Description These devices are identical in pinout to the 5 4 /7 4 L S 7 4 . They consist of two D-type flip-flops with individual preset, clear, and clock inputs. Infor­ mation at a D-input is transferred to the correspon­


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    PDF GD54/74HC74, GD54/74HCT74 54/74LS74. 74HC74 74ls74 timing setup hold 74hc74 pin diagram 74LS74 PINOUT 74HC74 pin configuration 74hct74 Current 74HCT74 TTL 74hc74 74HC GD74HCT74

    Untitled

    Abstract: No abstract text available
    Text: 74HC/HCT4538 MSI D U A L RETRIGGERABLE PRECISION MONOSTABLE MULTIVIBRATOR FEATURES T Y P IC A L • Separate reset inputs • Triggering from leading or trailing edge SYM BO L • Output capability: standard • Iq C category: MSI tP H L / tPLH propagation delay


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    PDF 74HC/HCT4538 CT4538

    74HC

    Abstract: 74HCT
    Text: 74HC/HCT390 MSI D U A L D E C A D E RIPPLE C O U N T E R F E A TU R E S Tw o BCD decade or bi-quinary counters • One package can be configured to divide-by-2,4 , 5 , 1 0 , 2 0 , 2 5 , 5 0 or 100 • Tw o master reset inputs to clear each decade counter individually


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    PDF 74HC/HCT390 74HC/HCT390 74HC 74HCT

    Untitled

    Abstract: No abstract text available
    Text: GD54/74HC107, GD54/74HCT107 DUAL J-K FLIP-FLOPS WITH CLEAR General Description These devices are identical in pinout to the 5 4 /7 4 L S 1 0 7 . They consist of two J-K flip-flops with individual J, K, clock, and clear inputs. These flipflops are edge sensitive to the clock input and


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    PDF GD54/74HC107, GD54/74HCT107

    Untitled

    Abstract: No abstract text available
    Text: GD54/74HC423, GD54/74HCT423 DUAL RETRIGGERABLE MONOSTABLE MULTIVIBRATORS General Description The d e v ic e s a re id e n tic a l in p in o u t to th e Pin Configuration 5 4 / 7 4 L S 4 2 3 . T h e y c o n s is t o f tw o re trig g e ra b le m o n o s ta b le


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    PDF GD54/74HC423, GD54/74HCT423 GD74HCT423 GD54HCT423

    74HC-HCT390

    Abstract: bcd decade counter ttl 74HC 74HCT
    Text: 74HC/HCT390 MSI DUAL DECADE RIPPLE COUNTER FEATURES • Two BCD decade or bi-quinary counters • One package can be configured to divide-by-2,4, 5 ,1 0 ,2 0 ,2 5 , 50 or 100 • Two master reset inputs to clear each decade counter individually • Output capability: standard


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    PDF 74HC/HCT390 74HC/HCT390 74HC-HCT390 bcd decade counter ttl 74HC 74HCT

    Untitled

    Abstract: No abstract text available
    Text: GD54/74HC73, GD54/74HCT73 DUAL J-K FLIP-FLOPS WITH CLEAR General Description These devices are identical in pinout to the 5 4 /7 4 L S 7 3 . These flip-flops are edge sensitive to the clock input and change state on the negative go­ ing transition of the clock pulse. Each flip-flop has


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    PDF GD54/74HC73, GD54/74HCT73