ICS93V850YGT Search Results

ICS93V850YGT Datasheets (1)

Part	ECAD Model	Manufacturer	Description	Curated	Datasheet Type	PDF
ICS93V850YGT		Integrated Circuit Systems	DDR Phase Lock Loop Clock Driver		Original	PDF

ICS93V850YGT Datasheets Context Search

Catalog Datasheet	MFG & Type	PDF	Document Tags
ICS93V850 Abstract: TSSOP48 Text: ICS93V850 Integrated Circuit Systems, Inc. Preliminary Product Preview DDR Phase Lock Loop Clock Driver Recommended Application: DDR Clock Driver Pin Configuration Switching Characteristics: • PEAK - PEAK jitter 66MHz : <120ps • PEAK - PEAK jitter (>100MHz): <75ps	Original	PDF	ICS93V850 66MHz) 120ps 100MHz) 100ps O-153 ICS93V850 TSSOP48
Untitled Abstract: No abstract text available Text: ICS93v850 Integrated Circuit Systems, Inc. Preliminary Product Preview DDR Phase Lock Loop Clock Driver Recommended Application: DDR Clock Driver Pin Configuration GND CLKC0 CLKT0 VDD CLKT1 CLKC1 GND GND CLKC2 CLKT2 VDD SCLK CLK_INT CLK_INC 2 VDDI C AVDD AGND	Original	PDF	ICS93v850 66MHz) 120ps 100MHz) 100ps 650ps 950ps
Untitled Abstract: No abstract text available Text: ICS93v850 Integrated Circuit Systems, Inc. Preliminary Product Preview DDR Phase Lock Loop Clock Driver Recommended Application: DDR Clock Driver Pin Configuration GND CLKC0 CLKT0 VDD CLKT1 CLKC1 GND GND CLKC2 CLKT2 VDD SCLK CLK_INT CLK_INC 2 VDDI C AVDD AGND	Original	PDF	ICS93v850 66MHz) 120ps 100MHz) 100ps 650ps 950ps
Untitled Abstract: No abstract text available Text: ICS93V850 Integrated Circuit Systems, Inc. Preliminary Product Preview DDR Phase Lock Loop Clock Driver Recommended Application: DDR Clock Driver Pin Configuration Switching Characteristics: • PEAK - PEAK jitter 66MHz : <120ps • PEAK - PEAK jitter (>100MHz): <75ps	Original	PDF	ICS93V850 66MHz) 120ps 100MHz) 100ps O-153 ICS93V850yGT
ICS93V850 Abstract: TSSOP48 Text: ICS93v850 Integrated Circuit Systems, Inc. Preliminary Product Preview DDR Phase Lock Loop Clock Driver Recommended Application: DDR Clock Driver Pin Configuration GND CLKC0 CLKT0 VDD CLKT1 CLKC1 GND GND CLKC2 CLKT2 VDD SCLK CLK_INT CLK_INC 2 VDDI C AVDD AGND	Original	PDF	ICS93v850 66MHz) 120ps 100MHz) 100ps 650ps 950ps ICS93V850 TSSOP48
Untitled Abstract: No abstract text available Text: ICS93V850 Integrated Circuit Systems, Inc. Preliminary Product Preview DDR Phase Lock Loop Clock Driver Recommended Application: DDR Clock Driver Pin Configuration Switching Characteristics: • PEAK - PEAK jitter 66MHz : <120ps • PEAK - PEAK jitter (>100MHz): <75ps	Original	PDF	ICS93V850 66MHz) 120ps 100MHz) 100ps 93V850D 93V850DGT