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    IKOS SYSTEMS Search Results

    IKOS SYSTEMS Result Highlights (5)

    Part ECAD Model Manufacturer Description Download Buy
    CS-VHDCIMX200-003 Amphenol Cables on Demand Amphenol CS-VHDCIMX200-003 VHDCI SCSI (SCSI-5) LVD/SE Cable - .8mm 68-pin VHDCI SCSI Male to Male 3m Datasheet
    CS-VHDCIMX200-000.5 Amphenol Cables on Demand Amphenol CS-VHDCIMX200-000.5 VHDCI SCSI (SCSI-5) LVD/SE Cable - .8mm 68-pin VHDCI SCSI Male to Male .5m Datasheet
    CS-VHDCIMX200-005 Amphenol Cables on Demand Amphenol CS-VHDCIMX200-005 VHDCI SCSI (SCSI-5) LVD/SE Cable - .8mm 68-pin VHDCI SCSI Male to Male 5m Datasheet
    CS-VHDCIMX200-006 Amphenol Cables on Demand Amphenol CS-VHDCIMX200-006 VHDCI SCSI (SCSI-5) LVD/SE Cable - .8mm 68-pin VHDCI SCSI Male to Male 6m Datasheet
    CS-VHDCIMX200-001 Amphenol Cables on Demand Amphenol CS-VHDCIMX200-001 VHDCI SCSI (SCSI-5) LVD/SE Cable - .8mm 68-pin VHDCI SCSI Male to Male 1m Datasheet

    IKOS SYSTEMS Datasheets Context Search

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    XC4000

    Abstract: JAEGER
    Text: XC4000 FPGA Provides IKOS with Increased Capacity for Third-Generation Emulator Page 1 of 2 Customer Success - IKOS XC4000 FPGA Provides IKOS with Increased Capacity for Third-Generation Emulator "Because it is a high density, high capacity device, the Xilinx FPGA allows us to provide very large capacity


    Original     		PDF XC4000 JAEGER

    ic 74151

    Abstract: pin configuration IC 74151 MSM10S0000 MSM10S0050 MSM10S0110 MSM10S0210 MSM10S0300 MSM10S0570 MSM10S0980 base cell
    Text: DATA SHEET O K I A S I C P R O D U C T S MSM10S0000 0.8 µm Sea of Gates Family 3-V and 5-V Applications December 1997 TRADEMARKS DAZIX and Advansys are trademarks of Intergraph, Inc. IKOS is a trademark of IKOS Systems, Inc. Mentor Graphics, Parade and Idea are trademarks of Mentor Graphics Corporation


    Original     		PDF MSM10S0000 1-800-OKI-6994 ic 74151 pin configuration IC 74151 MSM10S0000 MSM10S0050 MSM10S0110 MSM10S0210 MSM10S0300 MSM10S0570 MSM10S0980 base cell

    XC5200

    Abstract: No abstract text available
    Text: Edway Design Systems System Explorer ASIC Explorer XILLAS Concept Composer Verilog FPGA Designer Synergy Design Works TimingDesigner ALPS LSI Technologies Aptix Corporation Logical Devices Mentor Graphics ITS Logic Modeling Corp. Synopsis Division INCASES Engineering


    Original     		PDF RS6000 XC5200

    144 QFP body size

    Abstract: 35x35 bga BGA and QFP Package vhdl code for usart DesignWare SPI 0.18-um CMOS technology characteristics ARM7 verilog code NEC-V850 PZT driver design vhdl coding for analog to digital converter
    Text: GS20 0.18-µm CMOS Standard Cell/Gate Array Version 1.0 April 6, 1999 Copyright  Texas Instruments Incorporated, 1999 The information and/or drawings set forth in this document and all rights in and to inventions disclosed herein and patents which might be granted thereon disclosing or employing the


    Original     		PDF

    NEC-V850

    Abstract: DesignWare SPI vhdl code for watchdog timer of ATM ARM dual port SRAM compiler vhdl coding for analog to digital converter LogicVision verilog for SRAM 512k word 16bit uart verilog lvds synopsys on-chip modeling
    Text: GS30 0.15-µm CMOS Standard Cell/Gate Array Version 1.0 February, 2001 Copyright  Texas Instruments Incorporated, 2001 The information and/or drawings set forth in this document and all rights in and to inventions disclosed herein and patents which might be granted thereon disclosing or employing the


    Original     		PDF SRST145 NEC-V850 DesignWare SPI vhdl code for watchdog timer of ATM ARM dual port SRAM compiler vhdl coding for analog to digital converter LogicVision verilog for SRAM 512k word 16bit uart verilog lvds synopsys on-chip modeling

    verilog code for 32 bit risc processor

    Abstract: vhdl code for usart 35x35 bga Sun Enterprise 250 Sun Ultra 30 DesignWare SPI 0.18 um CMOS free vhdl code download for usart NEC-V850 PZT driver design
    Text: GS30TR 0.15-µm CMOS Standard Cell/Gate Array Version 1.0 September 23, 1999 Copyright  Texas Instruments Incorporated, 1999 The information and/or drawings set forth in this document and all rights in and to inventions disclosed herein and patents which might be granted thereon disclosing or employing the


    Original     		PDF GS30TR verilog code for 32 bit risc processor vhdl code for usart 35x35 bga Sun Enterprise 250 Sun Ultra 30 DesignWare SPI 0.18 um CMOS free vhdl code download for usart NEC-V850 PZT driver design

    ARM dual port SRAM compiler

    Abstract: designware i2c verilog code voltage regulator NEC-V850 ARM10 ARM946 TMS320C54X fastscan TI ASIC gs40 LogicVision
    Text: GS40 0.11-µm CMOS Standard Cell/Gate Array Version 1.0 January 29, 2001 Copyright  Texas Instruments Incorporated, 2001 The information and/or drawings set forth in this document and all rights in and to inventions disclosed herein and patents which might be granted thereon disclosing or employing the


    Original     		PDF SRST143 ARM dual port SRAM compiler designware i2c verilog code voltage regulator NEC-V850 ARM10 ARM946 TMS320C54X fastscan TI ASIC gs40 LogicVision

    ahb arbiter in mentor

    Abstract: 16x16x1.4
    Text: GS40 0.11-µm CMOS Standard Cell/Gate Array Version 0.5 May 19, 2000 Copyright  Texas Instruments Incorporated, 2000 The information and/or drawings set forth in this document and all rights in and to inventions disclosed herein and patents which might be granted thereon disclosing or employing the


    Original     		PDF

    UART TTL buffer

    Abstract: MSM10S0000 MSM10S0050 MSM10S0110 MSM10S0210 MSM10S0300 MSM10S0570 MSM10S0980 AMBIT inverter base cell
    Text: DATA SHEET O K I A S I C P R O D U C T S 0.8 µm Sea of Gates MSM10S Family 3-V and 5-V Applications August 2002 • Sea of Gates • MSM10S ■ ———————————————————————————————————— TRADEMARKS


    Original     		PDF MSM10S UART TTL buffer MSM10S0000 MSM10S0050 MSM10S0110 MSM10S0210 MSM10S0300 MSM10S0570 MSM10S0980 AMBIT inverter base cell

    38S02

    Abstract: ipad data sheet MSM38S0000 MSM98S MSM98S000
    Text: DATA SHEET O K I A S I C P R O D U C T S 0.8µm Mixed 3-V/5-V MSM38S0000 Sea of Gates and MSM98S000 Customer Structured Arrays February 1995 TRADEMARKS AIX, DOS, PC, and Windows are trademarks, and IBM is a registered trademark of IBM Corporation Apollo, Domain, and DomainOS are trademarks of Apollo Computer, a subsidiary of Hewlett-Packard


    Original     		PDF MSM38S0000 MSM98S000 1-800-OKI-6388 38S02 ipad data sheet MSM98S

    verilog code for UART with BIST capability

    Abstract: VHDL CODE FOR HDLC controller ARM dual port SRAM compiler DesignWare SPI vhdl code for watchdog timer of ATM vhdl coding for analog to digital converter Sun Enterprise 250 static SRAM single-port verilog code for 16 bit risc processor verilog code arm processor
    Text: GS30 0.15-µm CMOS Standard Cell/Gate Array Version 0.2 May 16, 2000 Copyright  Texas Instruments Incorporated, 2000 The information and/or drawings set forth in this document and all rights in and to inventions disclosed herein and patents which might be granted thereon disclosing or employing the


    Original     		PDF

    TOSHIBA TC160G

    Abstract: Toshiba NAND 67 Bga 568ps tc160g TC190G04 tc170g TC190G TC190G02 TC190G10 C2878
    Text: TOSHIBA System ASIC TC190 Series CMOS ASICs 0.6µ 3.0/3.3V ASIC Family The 0.6µm, 5V TC190 ASIC series provides higher system performance and device integration with lower power than previous generation 5V families. Highly accurate delay models, area efficient memory cells and a very fine pitch TAB bonding capability


    Original     		PDF TC190 TC190G) TC190E) TC190C) TC190E TOSHIBA TC160G Toshiba NAND 67 Bga 568ps tc160g TC190G04 tc170g TC190G TC190G02 TC190G10 C2878

    toshiba TC200

    Abstract: toshiba TC200C TOSHIBA GATE ARRAY Toshiba BGA 224 TC200E TC200 TC200C02 TC200G Edison time delay TC180
    Text: TOSHIBA System ASIC TC200 Series CMOS ASICs 0.4µ 3.0/3.3V ASIC Family The TC200 series is a family of 0.4µm, 3.0/3.3V ASICs. They are the first of a new generation of deep sub-micron “System ASIC” products with highly accurate delay models, area efficient memory cells and a very fine pitch TAB bonding capability for high


    Original     		PDF TC200 TC200G) TC200E) TC200C) TC200E toshiba TC200 toshiba TC200C TOSHIBA GATE ARRAY Toshiba BGA 224 TC200C02 TC200G Edison time delay TC180

    verilog code voltage regulator

    Abstract: verilog code for 32 bit risc processor vhdl code for watchdog timer of ATM fastscan verilog code for 16 bit risc processor NET 1672 analog to digital converter verilog Multi-Channel DMA Controller verilog code arm processor Texas Instruments I2C
    Text: GS30TR 0.15-µm CMOS Standard Cell/Gate Array Version 1.2 May 17, 2000 Copyright  Texas Instruments Incorporated, 2000 The information and/or drawings set forth in this document and all rights in and to inventions disclosed herein and patents which might be granted thereon disclosing or employing the


    Original     		PDF GS30TR verilog code voltage regulator verilog code for 32 bit risc processor vhdl code for watchdog timer of ATM fastscan verilog code for 16 bit risc processor NET 1672 analog to digital converter verilog Multi-Channel DMA Controller verilog code arm processor Texas Instruments I2C

    verilog code for UART with BIST capability

    Abstract: vhdl code for 8 to 3 encoder using concurrent sta 2 port register file open LVDS deserialization IP OC768 ARM10 ARM946 SR40 TLK2201 verilog code for ahb bus slave
    Text: SR40 0.095-µm High-Speed Copper Standard Cell/Gate Array ASIC Version 1.1 May 17, 2001 Copyright  Texas Instruments Incorporated, 2001 The information and/or drawings set forth in this document and all rights in and to inventions disclosed herein and patents which might be granted thereon disclosing or employing the


    Original     		PDF 24-hour verilog code for UART with BIST capability vhdl code for 8 to 3 encoder using concurrent sta 2 port register file open LVDS deserialization IP OC768 ARM10 ARM946 SR40 TLK2201 verilog code for ahb bus slave

    datasheet of BGA Staggered pins

    Abstract: NEC-V850 VHDL CODE FOR HDLC controller vhdl code for 4 channel dma controller clock tree balancing serdes transceiver 1999 verilog code for i2c vhdl code download for memory in cam vhdl code for watchdog timer of ATM vhdl coding for analog to digital converter
    Text: GS30 0.15-µm CMOS Standard Cell/Gate Array High-Value ASIC ❑ 0.15-µm Leff process 0.18-µm drawn with Shallow Trench Isolation (STI) Inline bond pads Minimum height I/Os Minimum width I/O ❑ 4 and 5 levels of metal ❑ 6 million random logic gates plus 6 million


    Original     		PDF

    TTL 740 NAND propagation delay

    Abstract: NA51 equivalent transistor AMI8G65 OB83 G392 IB09X1 MG82C54 MICROCONTROLLER-8051 NA21 na52 transistor
    Text: "AMI’s 0.8µm Gate Array family is simply the best 0.8µm on the market . . . one of the highest performance, yet lowest cost array products available today . . ." • Designed for 3V, 5V, or 3V/5V mixed supplies ■ 210 ps gate delays fanout = 2 ■ 5,000 to 663,000 available gate densities


    Original     		PDF

    L9013Q13Q

    Abstract: MSM13Q floorplan io uart vhdl
    Text: MSM13Q0000/14Q0000 0.35 µm Sea of Gates Arrays DESCRIPTION Oki’s 0.3 5 µm ASIC products deliver ultra-high performance and high density at low power dissipation. The MSM13Q0000/14Q0000 series devices referred to as “MSM13Q/14Q” are implemented with the


    Original     		PDF MSM13Q0000/14Q0000 MSM13Q0000/14Q0000 MSM13Q/14Q" MSM13Q) MSM14Q) 64-Mbit MSM13Q/14Q 1-800-OKI-6994 L9013Q13Q MSM13Q floorplan io uart vhdl

    ic 74151

    Abstract: ic 74163 oki cross MSM92RB01 MSM92RB02 msm32r0120 oki 82c54 82C54 oki of ic 74151 30R06
    Text: MSM30R0000/MSM32R0000/MSM92R000 Second-Generation 0.5µm Sea of Gates and Customer Structured Arrays DESCRIPTION Oki's second-generation 0.5µ m ASIC products are available in both Sea Of Gates SOG and Customer Structured Array (CSA) architectures. The MSM30R Series, MSM32R Series, and MSM92R Series all offer


    Original     		PDF MSM30R0000/MSM32R0000/MSM92R000 MSM30R MSM32R MSM92R adap88 92R126x126 ic 74151 ic 74163 oki cross MSM92RB01 MSM92RB02 msm32r0120 oki 82c54 82C54 oki of ic 74151 30R06

    Untitled

    Abstract: No abstract text available
    Text: ASICs H Supports • S u p p o rt Tools on Sale 9 IDEA Mentor Graphics Corp # DAZIX (DAZIX An Intergraph Company) # HP/EDS (Hewlett-packard) # CR3000/EDS # Composer (Cadence design systems inc.) # Workview (Viewlogic systems inc.) # CR3000/Workview # GRAG


    OCR Scan     		PDF CR3000/EDS CR3000/Workview

    ASIC CADENCE TOOL

    Abstract: No abstract text available
    Text: ASIC •Supports # EDA tool Support Condition \ Gate Arrays Type Channel type Tool Name \ MN56000 (as of September 1996) Sea-of-Gate (Channel-less type) MN56A00 MN56E00 Synopsys o O Verilog-XL o o VCS o o MOTIVE IDEA V8 O' o IDEA V7 o o Workview Q o PLUS


    OCR Scan     		PDF MN56000 MN56A00 MN56E00 MN5AA000 MN5C000 MN76000 MN7B000 MN7C000 MN7D000 ASIC CADENCE TOOL

    Untitled

    Abstract: No abstract text available
    Text: ASIC • Supports • Support conditions Type Tool Name Mentor V7 as of September 1995 FPGA Sea-of-Gate (Channel-less type) MN53000 MN56000 MN59000 MN56A00 MN56E00 MN5AA000 A ’3 O O O O Acte I EWS Gate Arrays (Channel type) Standard Cells MN5BA000 MN76000


    OCR Scan     		PDF MN53000 MN56A00 MN56E00 MN7A000 MN56000 MN59000 MN5AA000 MN5BA000 MN76000 MN7B000

    34992

    Abstract: SSC5100 F232-10 pinpad 78568
    Text: S-n 0 S SYSTEMS INC 5bE D • 7 cï 3 S tl D c1 G ODI Sb b SSC5000 'Ib? M S MO Series 0.8u HIGH SPEED CMOS STANDARD CELL SERIES° 7 ■ DESCRIPTION The S-MOS SSC5000 standard cell series is a 0.8 micron drawn family of standard cell circuits. It is manufactured on S-MOS’ state-of-the-art 0.8 micron double-metal N-well CMOS process. It Is comprised of 20


    OCR Scan     		PDF SSC5000 SSC5000 SSC50LQ C-115 34992 SSC5100 F232-10 pinpad 78568

    Untitled

    Abstract: No abstract text available
    Text: Oki Semiconductor MSM13Q/14Q 0.35 |im Sea of Gates Arrays DESCRIPTION Oki's 0.3 5 Jim ASIC products deliver ultra-high performance and high density at low power dissipation. The M SM 13Q0000/14Q0000 series devices referred to as "M SM 13Q /14Q " are implemented with the


    OCR Scan     		PDF MSM13Q/14Q 13Q0000/14Q0000 MSM13Q) MSM14Q) 64-Mbit 13Q/14Q 28x28 32x32