Untitled
Abstract: No abstract text available
Text: iniUTOPIA RX/TX and Inicore, a CoreHDL Partner Asynchronous Transfer Mode ATM Interface Features • • • • • • • • • • • General Description UTOPIA is a common interface in Asynchronous Transfer Mode (ATM) subsystems defined by the ATM Forum. The iniUTOPIA core
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alarm clock verilog code
Abstract: automatic alarm verilog code
Text: Datasheet RTC MODULE Version 1.0.1 INICORE INC. 5600 Mowry School Road Suite 180 Newark, CA 94560 t: 510 445 1529 f: 510 656 0995 e: info@inicore.com www.inicore.com COPYRIGHT 2003 INICORE INC. RTCmodule Datasheet Table of Contents 1
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RTSX72S
Abstract: A24D16 vmebus vhdl vhdl code for door vme bus interface verilog APA150 BU D16 vmebus controller vhdl testbench code vhdl synchronous parallel bus SX32A-3
Text: Optimized for VME A24D16 Slave Controller Description Features The VMEbus was first standardized in 1981 and is still in wide use. With the advances in integration technologies, custom integrated VME controllers open the door for smaller and cheaper systems. Inicore offers a wide range of different VME
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A24D16
1-199cess
Sept/2003
RTSX72S
vmebus vhdl
vhdl code for door
vme bus interface verilog
APA150
BU D16
vmebus controller vhdl testbench code
vhdl synchronous parallel bus
SX32A-3
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vhdl code for door
Abstract: RTSX72 vhdl synchronous parallel bus APA600 VME64 interrupt controller verilog code interrupt controller verilog 656 fpga vmebus controller vhdl testbench code
Text: Optimized for VME64 Slave Controller Description Features The VMEbus was first standardized in 1981 and is still in wide use. With the advances in integration technologies, custom integrated VME controllers open the door for smaller and cheaper systems. Inicore offers a wide range of different VME
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VME64
Sept/2003
vhdl code for door
RTSX72
vhdl synchronous parallel bus
APA600
interrupt controller verilog code
interrupt controller verilog
656 fpga
vmebus controller vhdl testbench code
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automotive canbus
Abstract: 128x11
Text: iniCAN Controller Area Network Interface and Inicore, a CoreHDL Partner Features • • • • • • • • General Description CANbus 2.0B, originally developed for the European car industry, is a fast, secure, and cost-effective data bus for multi-master and realtime applications. In addition to automotive applications, it is suitable
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automotive canbus
128x11
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Untitled
Abstract: No abstract text available
Text: iniG704-E1 Universal ISDN E1 Framer and Inicore, a CoreHDL Partner Features • • • • • • • • • • • • General Description The iniG704-E1 framer core is designed to structure data flows in ISDN systems for the telecommunications market. It’s a universal
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iniG704-E1
iniG704-E1
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vme vhdl
Abstract: APA150
Text: Optimized for VME A32D32 Slave Controller Description Features The VMEbus was first standardized in 1981 and is still in wide use. With the advances in integration technologies, custom integrated VME controllers open the door for smaller and cheaper systems. Inicore offers a wide range of different VME
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A32D32
Sept/2003
vme vhdl
APA150
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Untitled
Abstract: No abstract text available
Text: iniSCI I2C Bus Controller Interface and Inicore, a CoreHDL Partner Features • I2C-Compatible • Single Master • Programmable Baud Rate Generator 390–100 kbps with 1µs Clock Enable • Automatically Incremented Address Pointer • 3-Point Input Sampling, Glitch Rejection
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3200DX,
1200XL,
5172128-0F
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VERILOG Digitally Controlled Oscillator
Abstract: vhdl code for DCO verilog code for uart apb vhdl code for 4 bit even parity generator uart verilog code vhdl code for 8 bit ODD parity generator uart vhdl code fpga
Text: D a ta s h e e t UART MODULE Revision 2.8.1 INICORE INC. 5600 Mowry School Road Suite 180 Newark, CA 94560 t: 510 445 1529 f: 510 656 0995 e: info@inicore.com www.inicore.com C O P Y R IG H T 2 0 0 1 - 2 0 0 4 , IN IC O R E , IN C . U A R T m o d u le D a ta s h e e t
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programming logic controller
Abstract: 14 pin gpio port GPIO verilog code for apb Inicore
Text: Datasheet GPIO MODULE Version 1.2 INICORE INC. 5600 Mowry School Road Suite 180 Newark, CA 94560 t: 510 445 1529 f: 510 656 0995 e: info@inicore.com www.inicore.com COPYRIGHT 2003 INICORE INC. GPIOmodule Datasheet Table of Contents 1
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Untitled
Abstract: No abstract text available
Text: Datasheet CANmodule-IIx Version 2.6.2 INICORE INC. 5600 Mowry School Road Suite 180 Newark, CA 94560 t: 510 445 1529 f: 510 656 0995 e: info@inicore.com www.inicore.com 2002-2004, INICORE, INC. CANmodule-IIx Datasheet Table Of Contents 1
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AT91R40807
Abstract: P1386 Silicon Sculptor II sdb 750 pc100 system board sram 16 mbyte
Text: System-on-Chip from Spec to Silicon System Design Board SDB-750/1000 Features Product Description Inicore's System Design Board SDB-1000 provides a versatile platform for your next development. An ARM based CPU subsystem with 2 MBytes of SRAM and 16 MBytes of program
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SDB-750/1000
SDB-1000
198K-bits
RS-232
com/sdb-750/1000
AT91R40807
P1386
Silicon Sculptor II
sdb 750
pc100 system board
sram 16 mbyte
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EG125
Abstract: No abstract text available
Text: iniUART and Inicore, a CoreHDL Partner Universal Asynchronous Receiver/Transmitter Features • Configurable Transfer Rate: 1200 bps to 64 kbps with Accuracy Better than 0.1% from 8 MHz Clock • Data Format: 7 or 8 Bits • Parity Enable, Odd/Even, Parity Error Detection
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1200XL,
RS-232
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ISO-118980-1
Abstract: No abstract text available
Text: Datasheet iniCAN C ONTROLLER A REA N ETWORK PROTOCOL CONTROLLER Revision 2.0 INICORE INC. 5600 Mowry School Road Suite 180 Newark, CA 94560 t: 510 445 1529 f: 510 656 0995 e: info@inicore.com www.inicore.com COPYRIGHT 2001-2010 INICORE INC. iniCAN Datasheet
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verilog code for slave SPI with FPGA
Abstract: vhdl code for spi vhdl spi interface VHDL code for slave SPI with FPGA SPI Timing Diagram
Text: Datasheet SPIM MODULE Revision 2.2 INICORE INC. 5600 Mowry School Road Suite 180 Newark, CA 94560 t: 510 445 1529 f: 510 656 0995 e: info@inicore.com www.inicore.com COPYRIGHT 2002-2003, INICORE INC. SPIMmodule Datasheet Table of Contents 1
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vme bus specification
Abstract: VMEL VME64 VME64S D64-MBLT VME64-M vme core VME/ST6398
Text: Datasheet VME64M VME64 M ASTER C ONTROLLER Version 1.1 INICORE INC. 5600 Mowry School Road Suite 180 Newark, CA 94560 t: 510 445 1529 f: 510 656 0995 e: info@inicore.com www.inicore.com COPYRIGHT 2007-2008, INICORE INC. VME64M Datasheet Ta b l e o f C o n t e n t s
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VME64M
VME64
vme bus specification
VMEL
VME64S
D64-MBLT
VME64-M
vme core
VME/ST6398
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vhdl code for Clock divider for FPGA
Abstract: AMBA BUS vhdl code
Text: Datasheet TIMER MODULE Version 1.2.1 INICORE INC. 5600 Mowry School Road Suite 180 Newark, CA 94560 t: 510 445 1529 f: 510 656 0995 e: info@inicore.com www.inicore.com COPYRIGHT 2003 INICORE INC. TIMERmodule Datasheet Table of Contents 1
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ISO 11898-1
Abstract: round robin bus arbitration ROUND ROBIN ARBITRATION AND FIXED PRIORITY SCHEME CANopen
Text: Datasheet CANmodule-III Version 2.2.1 INICORE INC. 5600 Mowry School Road Suite 180 Newark, CA 94560 t: 510 445 1529 f: 510 656 0995 e: info@inicore.com www.inicore.com 2002-2004, INICORE, INC. CANmodule-III Datasheet Table Of Contents 1
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baudrate
Abstract: UART DESIGN
Text: iniUART data sheet Features: • Configurable Transfer Rate: 1200bps to 115.2kbps with Accuracy Better than 0.1% from 8MHz Clock! • Data Format: 7, 8 Bits • Parity Enable, Odd/Even, Error Detection • Stop Bit: 1, 2 Bits • Format Check • 3-Point Input Sampling, Glitch Rejection
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391-DS-14
baudrate
UART DESIGN
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phase detector in RTL
Abstract: ADPLL phase detector CH-2555 ADPLL with low jitter
Text: iniADPLL All Digital Phase Locked Loop Features • • • • • • • • • General Description The iniADPLL is an all digital implementation of a phase locked loop. PLLs are widely used in telecom applications for clock recovery, clock generation and clock supervision. The all digital solution needs no external
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BOSCH CAN
Abstract: DLC3 BOSCH CAN vhdl id28 PCA82C250T ID-28 DLC2
Text: iAP-CANaccess APB t lian p m o c data sheet A AMB Features: • CAN 2.0B, up to 1Mbit/s • Trace Capability on Bit Level • AMBA (APB) compliant interface • Access to all Internal Status, Error Counters • Frame Reference, TX Bus, RX Bus internally and externally available (FIFO
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PCA82C250T
BOSCH CAN
DLC3
BOSCH CAN vhdl
id28
PCA82C250T
ID-28
DLC2
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BOSCH fpg
Abstract: A32140DX PCA82C250T PQFP160 Bosch TMS
Text: CANaccess A FPG n o B . CAN2 data sheet Features: • CAN 2.0B, up to 1Mbit/s • Trace Capability on Bit Level • MC683xx compatible Interface 300 ns • Access to all Internal Status, Error Counters • Frame Reference, TX Bus, RX Bus internally and externally available (FIFO
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MC683xx
A32140DX
PQFP160
312-DS-12
BOSCH fpg
PCA82C250T
Bosch TMS
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ISO 11898-1
Abstract: Controller Area Network
Text: PSoC Creator Component Datasheet Controller Area Network CAN 2.30 Features • CAN2.0A and CAN2.0B protocol implementation, ISO 11898-1 compliant • Programmable bit rate up to 1 Mbps at 8 MHz (BUS_CLK) Two-wire or three-wire interface to external transceiver (Tx, Rx, and
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ISO 11898-1
Controller Area Network
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bosch motronic
Abstract: motronic bosch torque sensor bosch j1939 Bosch Washing machine CPU STARTER CUTLER HAMMER bosch washing machine motor bosch wheel speed sensor bosch injection cpu bosch motronic 1.3
Text: CONfROL ENGINEERING An Inside Look at the Fundamentals of CAN HOLGER ZELTWANGER. CAN in Automation Users and Manufacturers Group e.V. Erlangen. Germany intelligent I/O devices as well as sensors and actuators within a machine or plant. The textile machinery industry is one
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