INICORE Search Results
INICORE Datasheets (7)
Part |
ECAD Model |
Manufacturer |
Description |
Curated |
Datasheet Type |
PDF |
|---|---|---|---|---|---|---|
| CANaccess | Inicore | CAN2.0B on FPGA | Original | |||
| iAH-INTC32 | Inicore | AMBA (AHB) compliant, fully programmable interrupt controller with 32 interrupt sources. | Original | |||
| iAH-LCDC | Inicore | LCD controller | Original | |||
| iAP-CAN16f | Inicore | full CAN controller | Original | |||
| iniADPLL | Inicore | All Digital Phase Locked Loop | Original | |||
| iniCAN-Observer | Inicore | data link layer observer | Original | |||
| iniFUART | Inicore | Fast Universal Asynchronous Receiver Transmitter (FUART) | Original |
INICORE Datasheets Context Search
Catalog Datasheet |
Type |
Document Tags |
PDF |
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Contextual Info: iniUTOPIA RX/TX and Inicore, a CoreHDL Partner Asynchronous Transfer Mode ATM Interface Features • • • • • • • • • • • General Description UTOPIA is a common interface in Asynchronous Transfer Mode (ATM) subsystems defined by the ATM Forum. The iniUTOPIA core |
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16-Bit 5172125-0F | |
alarm clock verilog code
Abstract: automatic alarm verilog code
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RTSX72S
Abstract: A24D16 vmebus vhdl vhdl code for door vme bus interface verilog APA150 BU D16 vmebus controller vhdl testbench code vhdl synchronous parallel bus SX32A-3
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A24D16 1-199cess Sept/2003 RTSX72S vmebus vhdl vhdl code for door vme bus interface verilog APA150 BU D16 vmebus controller vhdl testbench code vhdl synchronous parallel bus SX32A-3 | |
vhdl code for door
Abstract: RTSX72 vhdl synchronous parallel bus APA600 VME64 interrupt controller verilog code interrupt controller verilog 656 fpga vmebus controller vhdl testbench code
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VME64 Sept/2003 vhdl code for door RTSX72 vhdl synchronous parallel bus APA600 interrupt controller verilog code interrupt controller verilog 656 fpga vmebus controller vhdl testbench code | |
automotive canbus
Abstract: 128x11
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5172126-1F automotive canbus 128x11 | |
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Contextual Info: iniG704-E1 Universal ISDN E1 Framer and Inicore, a CoreHDL Partner Features • • • • • • • • • • • • General Description The iniG704-E1 framer core is designed to structure data flows in ISDN systems for the telecommunications market. It’s a universal |
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iniG704-E1 iniG704-E1 5172127-0F | |
vme vhdl
Abstract: APA150
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A32D32 Sept/2003 vme vhdl APA150 | |
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Contextual Info: iniSCI I2C Bus Controller Interface and Inicore, a CoreHDL Partner Features • I2C-Compatible • Single Master • Programmable Baud Rate Generator 390–100 kbps with 1µs Clock Enable • Automatically Incremented Address Pointer • 3-Point Input Sampling, Glitch Rejection |
Original |
3200DX, 1200XL, 5172128-0F | |
VERILOG Digitally Controlled Oscillator
Abstract: vhdl code for DCO verilog code for uart apb vhdl code for 4 bit even parity generator uart verilog code vhdl code for 8 bit ODD parity generator uart vhdl code fpga
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programming logic controller
Abstract: 14 pin gpio port GPIO verilog code for apb Inicore
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Contextual Info: Datasheet CANmodule-IIx Version 2.6.2 INICORE INC. 5600 Mowry School Road Suite 180 Newark, CA 94560 t: 510 445 1529 f: 510 656 0995 e: info@inicore.com www.inicore.com 2002-2004, INICORE, INC. CANmodule-IIx Datasheet Table Of Contents 1 |
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AT91R40807
Abstract: P1386 Silicon Sculptor II sdb 750 pc100 system board sram 16 mbyte
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SDB-750/1000 SDB-1000 198K-bits RS-232 com/sdb-750/1000 AT91R40807 P1386 Silicon Sculptor II sdb 750 pc100 system board sram 16 mbyte | |
EG125Contextual Info: iniUART and Inicore, a CoreHDL Partner Universal Asynchronous Receiver/Transmitter Features • Configurable Transfer Rate: 1200 bps to 64 kbps with Accuracy Better than 0.1% from 8 MHz Clock • Data Format: 7 or 8 Bits • Parity Enable, Odd/Even, Parity Error Detection |
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3200DX, 1200XL, RS-232 5172124-1F EG125 | |
ISO-118980-1Contextual Info: Datasheet iniCAN C ONTROLLER A REA N ETWORK PROTOCOL CONTROLLER Revision 2.0 INICORE INC. 5600 Mowry School Road Suite 180 Newark, CA 94560 t: 510 445 1529 f: 510 656 0995 e: info@inicore.com www.inicore.com COPYRIGHT 2001-2010 INICORE INC. iniCAN Datasheet |
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verilog code for slave SPI with FPGA
Abstract: vhdl code for spi vhdl spi interface VHDL code for slave SPI with FPGA SPI Timing Diagram
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vme bus specification
Abstract: VMEL VME64 VME64S D64-MBLT VME64-M vme core VME/ST6398
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VME64M VME64 vme bus specification VMEL VME64S D64-MBLT VME64-M vme core VME/ST6398 | |
vhdl code for Clock divider for FPGA
Abstract: AMBA BUS vhdl code
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ISO 11898-1
Abstract: round robin bus arbitration ROUND ROBIN ARBITRATION AND FIXED PRIORITY SCHEME CANopen
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baudrate
Abstract: UART DESIGN
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1200bps 391-DS-14 baudrate UART DESIGN | |
phase detector in RTL
Abstract: ADPLL phase detector CH-2555 ADPLL with low jitter
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BOSCH CAN
Abstract: DLC3 BOSCH CAN vhdl id28 PCA82C250T ID-28 DLC2
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PCA82C250T BOSCH CAN DLC3 BOSCH CAN vhdl id28 PCA82C250T ID-28 DLC2 | |
BOSCH fpg
Abstract: A32140DX PCA82C250T PQFP160 Bosch TMS
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MC683xx A32140DX PQFP160 312-DS-12 BOSCH fpg PCA82C250T Bosch TMS | |
bosch motronic
Abstract: motronic bosch torque sensor bosch j1939 Bosch Washing machine CPU STARTER CUTLER HAMMER bosch washing machine motor bosch wheel speed sensor bosch injection cpu bosch motronic 1.3
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OCR Scan |
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ISO 11898-1
Abstract: Controller Area Network
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ISO-11898-1 ISO 11898-1 Controller Area Network | |