74F04
Abstract: 74F74 800E 801C T222 T225 T225E Inmos T222
Text: IMS T225 16-bit transputer FEATURES 16 bit architecture 33 ns internal cycle time 30 MIPS peak instruction rate Debugging support 4 Kbytes on-chip static RAM 60 Mbytes/sec sustained data rate to internal memory 64 Kbytes directly addressable external memory
|
Original
|
16-bit
74F04
74F74
800E
801C
T222
T225
T225E
Inmos T222
|
PDF
|
T222 transputer
Abstract: 74F74 800E 801C T222 T225 IMST222 T225E
Text: IMS T225E 16-bit transputer – Extended temperature FEATURES 16 bit architecture 50 ns internal cycle time 20 MIPS peak instruction rate Debugging support 4 Kbytes on-chip static RAM 40 Mbytes/sec sustained data rate to internal memory 64 Kbytes directly addressable external memory
|
Original
|
T225E
16-bit
T222 transputer
74F74
800E
801C
T222
T225
IMST222
T225E
|
PDF
|
74F74
Abstract: inmos transputer T225 transputer Inmos t805 FP 8022 74F04 800E 801C T222 T225
Text: IMS T225 16-bit transputer FEATURES H 16 bit architecture H 33 ns internal cycle time H 30 MIPS peak instruction rate H Debugging support H 4 Kbytes on-chip static RAM H 60 Mbytes/sec sustained data rate to internal memory H 64 Kbytes directly addressable external memory
|
Original
|
16-bit
74F74
inmos transputer T225
transputer
Inmos t805
FP 8022
74F04
800E
801C
T222
T225
|
PDF
|
T425
Abstract: T400 T414 T800 T805 inmos transputer T425 T800 transputer IMST425
Text: IMS T425 32-bit transputer FEATURES 32 bit architecture 40 ns internal cycle time 25 MIPS peak instruction rate Pin compatible with IMS T805, IMS T800, IMS T400 and IMS T414 Debugging support 4 Kbytes on-chip static RAM System Services 100 Mbytes/sec sustained data rate to internal
|
Original
|
32-bit
T425
T400
T414
T800
T805
inmos transputer T425
T800 transputer
IMST425
|
PDF
|
inmos T414
Abstract: inmos T400 12u-1919-g19 25f5 T400 600 inmos transputer T425 T400 clock T800 transputer AD T805 IMS T414
Text: IMS T400 Low cost 32-bit transputer FEATURES H 32 bit architecture H 50 ns internal cycle time H 20 MHz only H 20 MIPS peak instruction rate H 10 MIPS sustained instruction rate H Pin compatible with IMS T805, IMS T800, IMS T425 and IMS T414 H 2 Kbytes on-chip static RAM
|
Original
|
32-bit
inmos T414
inmos T400
12u-1919-g19
25f5
T400 600
inmos transputer T425
T400 clock
T800 transputer
AD T805
IMS T414
|
PDF
|
Inmos t805
Abstract: IMS T805-F20E T425 T800 IMST800 21-F5 REAL32
Text: IMS T805E 32-bit floating-point transputer – Extended temperature FEATURES APPLICATIONS Scientific and mathematical applications High speed multi processor systems High performance graphics processing – HUD/HDD displays Supercomputers Workstations and workstation clusters
|
Original
|
T805E
32-bit
Inmos t805
IMS T805-F20E
T425
T800
IMST800
21-F5
REAL32
|
PDF
|
Inmos t805
Abstract: IMS T805-G25S IMS T805-F25S IMS T800 T400 T414 T425 T800 T805 inmos T414
Text: IMS T805 32-bit floating-point transputer FEATURES Floating Point Unit 32 32 bit architecture 40 ns internal cycle time 25 MIPS peak instruction rate 3.6 Mflops (peak) instruction rate Pin compatible with IMS T800, IMS T425, IMS T400 and IMS T414 Debugging support
|
Original
|
32-bit
Inmos t805
IMS T805-G25S
IMS T805-F25S
IMS T800
T400
T414
T425
T800
T805
inmos T414
|
PDF
|
Untitled
Abstract: No abstract text available
Text: IMS T225 7 Links Four identical INMOS bi-directional serial links provide synchronised communication between processors and with the outside world. Each link comprises an input channel and output channel. A link between two transputers is implemented by connecting a link interface on one transputer to a link interface on the other
|
OCR Scan
|
|
PDF
|
inmos transputer T225
Abstract: IMST222
Text: 1 Introduction 1 Introduction The IMS T225 transputer is a 16 bit CMOS microcomputer with 4 Kbytes on-chip RAM for high speed pro cessing, an external memory interface and four standard INMOS communication links. The instruction set achieves efficient implementation of high level languages such as ANSI C and provides direct support for
|
OCR Scan
|
IMST225
inmos transputer T225
IMST222
|
PDF
|
D4205
Abstract: inmos m212 disk processor B4043 D42050 T225 D505A IMS B404 T414 D705B ims-m212
Text: Chapter 2 9 □ mos IMS D7205 IMS D6205 IMS D5205 IMS D4205 0 C C 3 IT I 2 Toolset Product Information occam cross-development systems for IBM PC, NEC PC, Sun 3, Sun 4 and VAX hosts KEY FEATURES • Occam compiler for INMOS transputer family of processors
|
OCR Scan
|
D7205
D6205
D5205
D4205
D5205
D6205
inmos m212 disk processor
B4043
D42050
T225
D505A
IMS B404
T414
D705B
ims-m212
|
PDF
|
T222-20
Abstract: inmos transputer T225 ims pcb B4301 IMSB430 B-430 B430TRAM T225
Text: Chapter 35 301 IMS B430 Prototyping TRAM mos FEATURES IMS T222 16-bit Transputer User programmable Wait State Generator Two JEDEC user configurable memory sock ets with 32Kbyte of SRAM fitted as standard Two memory mapped I/O control signals Large through-hole matrix prototyping area
|
OCR Scan
|
16-bit
32Kbyte
T222-20
B430-10
inmos transputer T225
ims pcb
B4301
IMSB430
B-430
B430TRAM
T225
|
PDF
|
inmos m212 disk processor
Abstract: T222 inmos T414 D5214 IMSB404 inmos transputer reference manual ims-m212 Transputer T414 nec pc9801
Text: Chapter 3 □ I mos* 23 IMS D7214 IMS D6214 IMS D5214 IMS D4214 ANSI C Toolset Product Information ANSI C cross-development systems for IBM PC, NEC PC, Sun 3, Sun 4 and VAX hosts KEY FEATURES • Full ANSI C compiler X3.159-1989 • Validated against Plum Hall validation suite
|
OCR Scan
|
D4214
DC600A
QIC-11,
QIC-24,
inmos m212 disk processor
T222
inmos T414
D5214
IMSB404
inmos transputer reference manual
ims-m212
Transputer T414
nec pc9801
|
PDF
|
Untitled
Abstract: No abstract text available
Text: SCS-IHOMSON -T/ M I » lgllljl5TnM0ieg IMS T225E 16-bit transputer - Extended temperature FEATURES • 16 bit architecture ■ 50 ns internal cycle time ■ 20 MIPS peak instruction rate ■ Debugging support ■ 4 Kbytes on-chip static RAM ■ 40 Mbytes/sec sustained data rate to internal memory
|
OCR Scan
|
T225E
16-bit
|
PDF
|
Untitled
Abstract: No abstract text available
Text: w# SGS-THOMSON IMS T225 16-bit transputer FEATURES • 16 bit architecture ■ 33 ns internal cycle time ■ 30 MIPS peak instruction rate ■ Debugging support ■ 4 Kbytes on-chip static RAM ■ 60 Mbytes/sec sustained data rate to internal memory ■ 64 Kbytes directly addressable external memory
|
OCR Scan
|
16-bit
|
PDF
|
|
T225E
Abstract: ST225
Text: w # S G S -m O M S O N IMS T225E 16-bit transputer - Extended temperature FEATURES • 16 bit architecture ■ 50 ns internal cycle time ■ 20 MIPS peak instruction rate ■ Debugging support ■ 4 Kbytes on-chip static RAM ■ 40 Mbytes/sec sustained data rate to internal memory
|
OCR Scan
|
T225E
16-bit
IMST400
T225E
ST225
|
PDF
|
Untitled
Abstract: No abstract text available
Text: SGS-THOMSON IMS T225 • H I 16-bit transputer EATURES 16 bit architecture 33 ns internal cycle time 30 MIPS peak instruction rate Debugging support 4 Kbytes on-chip static RAM 60 Mbytes/sec sustained data rate to internal memory 64 Kbytes directly addressable external memory
|
OCR Scan
|
16-bit
IMST400
|
PDF
|
inmos transputer T225
Abstract: inmos transputer T425 inmos T225 T400 clock transputer IMST222 2U06 T225 801C IMST225
Text: /^ T A S G S -T H O M S O N T Ë , « fô tm IMS T225 ilg ïïlîM Ig S 16-bit transputer FEATURES • 16 bit architecture ■ 33 ns internal cycle time ■ 30 MIPS peak instruction rate ■ Debugging support ■ 4 Kbytes on-chip static RAM ■ 60 Mbytes/sec sustained data rate to internal memory
|
OCR Scan
|
16-bit
71E1E37
inmos transputer T225
inmos transputer T425
inmos T225
T400 clock
transputer
IMST222
2U06
T225
801C
IMST225
|
PDF
|
CQ 2AF1
Abstract: IMST425 IMS T400 Inmos T222
Text: 32-bit transputer FEATURES • 32 bit architecture ■ 40 ns internal cycle time ■ 25 MIPS peak instruction rate ■ Pin compatible with IMS T805, IMS T800, IMS T400 and IMS T414 ■ Debugging support ■ 4 Kbytes on-chip static RAM ■ 100 Mbytes/sec sustained data rate to internal
|
OCR Scan
|
32-bit
CQ 2AF1
IMST425
IMS T400
Inmos T222
|
PDF
|
T225E
Abstract: imst225
Text: _ 16-bit transputer FEATURES • 16 bit architecture ■ 33 ns internal cycle time ■ 30 MIPS peak instruction rate ■ Debugging support ■ 4 Kbytes on-chip static RAM ■ 60 Mbytes/sec sustained data rate to internal memory ■
|
OCR Scan
|
16-bit
64rrs
71E1237
T225E
imst225
|
PDF
|
t425
Abstract: SGS thomson power schottky 8000000C sgs thomson 23-F1 KJH T6 IMST425 inmos transputer T425
Text: w # S G S -T H O M S O N IM < 5 , kT # D ïiin g M iiiL iK g T Â E g n e i ,M & _ T 4 2 5 32-bit transputer FEATURES 32 bit architecture 40 ns internal cycle time 25 MIPS peak instruction rate Pin compatible with IMS T805, IMS T800, IMST400 and IMS T414
|
OCR Scan
|
32-bit
MST400
PGA/84pin
PLCC/100
t425
SGS thomson power schottky
8000000C
sgs thomson
23-F1
KJH T6
IMST425
inmos transputer T425
|
PDF
|
sbl 20100
Abstract: T425-X25S MEMAD11 inmos transputer T425
Text: ^•7 # DMD g(fii ilL[l(gTO©[i!!in(gI / = T S G S -T H O M S O N IM S T 4 2 5 32-bit transputer FEATURES ■ 32 bit architecture ■ 40 ns internal cycle time ■ 25 MIPS peak instruction rate ■ Pin compatible with IMS T805, IMS T800, IMS T400 and IMS T414
|
OCR Scan
|
32-bit
sbl 20100
T425-X25S
MEMAD11
inmos transputer T425
|
PDF
|
IMST414
Abstract: IMS T400 ST T4 1060 0922 imst400 IMST225 inmos T414 T805-20 R3174 si9590 inmos transputer
Text: SGS-THOMSON IM S T 4 0 0 Low cost 32-bit transputer FEATURES • 32 bit architecture ■ 50 ns internal cycle time ■ 20 MHz only ■ 20 MIPS peak instruction rate ■ 10 MIPS sustained instruction rate ■ Pin compatible with IMS T805, IMS T800, IMS T425
|
OCR Scan
|
32-bit
IMST414
PLCC100/
IMS T400
ST T4 1060 0922
imst400
IMST225
inmos T414
T805-20
R3174
si9590
inmos transputer
|
PDF
|
T400 600
Abstract: IMS T414
Text: Low cost 32-bit transputer FEATURES • 32 bit architecture ■ 50 ns internal cycle time ■ 20 MHz only ■ 20 MIPS peak instruction rate ■ 10 MIPS sustained instruction rate ■ Pin compatible with IMS T805, IMS T800, IMS T425 and IMS T414 ■ 2 Kbytes on-chip static RAM
|
OCR Scan
|
32-bit
T400 600
IMS T414
|
PDF
|
Untitled
Abstract: No abstract text available
Text: S G S -1 H 0 M S 0 N « t i m i I g ï M a M Ê IMS T400 i Low cost 32-bit transputer FEATURES 32 bit architecture 50 ns internal cycle time 20 MHz only 20 MIPS peak instruction rate 10 MIPS sustained instruction rate Pin compatible with IMS T805, IMS T800, IMS T425
|
OCR Scan
|
32-bit
T00b2
|
PDF
|