386SX CIRCUIT diagram
Abstract: i386SX
Text: A m 386 S X ^ Advanced Micro Devices High-Performance, 32-Bit Microprocessor with 16-Bit Data Bus DISTINCTIVE CHARACTERISTICS • Com patible with 386SX system s and software ■ 25- and 20-M Hz operating speeds ■ Pin-for-pin replacem ent of the Intel I386SX
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386TM
32-Bit
16-Bit
386SX
I386SX
387SX-com
100-lead
24-blt
16-blt
Am386SX
386SX CIRCUIT diagram
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intel 8232
Abstract: MCS-80 MCS-85 MCS-86 3FF00000 s 8232 u s+8232+u
Text: in te i 8232 FLOATING POINT PROCESSING UNIT Standard 24-Pin Package Compatible with Proposed IEEE For mat and Existing Intel Floating Point Standard 12V and 5V Power Supplies Compatible with MCS-80 , MCS-85™ and MCS-86™ Microprocessor Families Single 32-Bit and Double (64-Bit)
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32-Bit)
64-Bit)
24-Pin
MCS-80â
MCS-85â
MCS-86â
01263B
intel 8232
MCS-80
MCS-85
MCS-86
3FF00000
s 8232 u
s+8232+u
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intel 8232
Abstract: No abstract text available
Text: in t e i 8232 FLOATING POINT PROCESSING UNIT Standard 24-Pin Package Compatible with Proposed IEEE For mat and Existing Intel Floating Point Standard 12V and 5V Power Supplies Compatible with MCS-80 , MCS-85™ and MCS-86™ Microprocessor Families Single 32-Bit and Double (64-Bit)
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24-Pin
MCS-80â
MCS-85â
MCS-86â
32-Bit)
64-Bit)
01263B
intel 8232
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intel microprocessor 32 bit pin diagram
Abstract: CY7C9536 CYS25G0101DX OC48 RXD14
Text: CY7C9536 Interfaces with CYS25G0101DX and Microprocessor Introduction Block Diagram The CY7C9536 POSIC Packet Over SONET/SDH IC is a highly integrated and sophisticated SONET/SDH frame device. It is used for the transport of ATM, HDLC, and GFP packets over SONET/SDH links. This device provides five interfaces to communicate to external peripherals. These five
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CY7C9536
CYS25G0101DX
intel microprocessor 32 bit pin diagram
OC48
RXD14
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LT249
Abstract: Intel overdrive
Text: ¡n t g l, Intel486 SX MICROPROCESSOR IMPORTANT—Read This Section Before Reading The Rest Of The Data Sheet This data sheet describes the Intel486 SX microprocessor, the Intel OverDriveTM Processor, and the Intel487™ SX Math Coprocessor. All normal text describes the functionality for the Intel486 SX microproces
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Intel486â
Intel486
Intel487â
Intel487
LT249
Intel overdrive
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d1277
Abstract: Intel overdrive
Text: INTEL CORP UP/PRPHLS b7E D • HÖ5bl7S D127bG3 3Ö1 in te i Intel486 SX MICROPROCESSOR IMPORTANT—Read This Section Before Reading The Rest Of The Data Sheet This data sheet describes the Intel486 SX microprocessor, the Intel OverDrive™ Processor, and the
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D127bG3
Intel486â
Intel486
lntel487TM
Intel487
2bl75
d1277
Intel overdrive
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Untitled
Abstract: No abstract text available
Text: DATA S H E E T M AY 1999 Revision 2.1 LXP710 HDSL Framer/Mapper for 1168 kbps Applications General Description The LXP710 is a complete HDSL framer/mapper that multiplexes and demultiplexes a framed or unframed 2.048 Mbps E l data stream onto two 1168 kbps H DSL lines. The LXP710 also
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LXP710
LXP710
SK70704/
SK70707
LXP710PE
84-pin
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i960 sb
Abstract: 32-bit microprocessor architecture applications of microprocessor in printer i960 kb i960 microprocessor control unit intel i960 intel i960 series i960CF
Text: i960 CA/i960 CF 32-Bit Superscalar Embedded Microprocessor Product Overview Product Highlights The i960 CA embedded RISC processor was introduced in September, 1989 as the world’s first superscalar 32-bit processor developed for embedded applications.
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CA/i960
32-Bit
32-bit
i960-282
0/0194/10K/HP
i960 sb
32-bit microprocessor architecture
applications of microprocessor in printer
i960 kb
i960 microprocessor control unit
intel i960
intel i960 series
i960CF
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Intel overdrive
Abstract: No abstract text available
Text: in t e i Intel486 SX M ICROPROCESSOR IM PORTANT— Read This Section Before Reading The Rest Of The Data Sheet This data sheet describes the Intel486 SX microprocessor, the Intel OverDrive™ Processor, and the l n t e l 4 8 7 TM S X Math Coprocessor. All normal text describes the functionality for the Intel486 SX microproces
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Intel486â
Intel486
Intel487
240950-D3
Intel overdrive
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Intel i860
Abstract: No abstract text available
Text: INTEL CORP UP/PRPHLS bflE » • 4ñ2bl7S Dia^flSb in te i i860 XR 64-BIT MICROPROCESSOR ■ Parallel Architecture that Supports Up to Three Operations per Clock — One Integer or Control Instruction per Clock — Up to Two Floating-Point Results per
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64-BIT
128-Bit
32-Bit
32/64-Bit
80860XR
Intel i860
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speed control of dc motor using scr mini project
Abstract: AUTOMATIC ROOM LIGHT CONTROLLER using ldr LED TV Screen working Theory AUTOMATIC ROOM LIGHT generator using ldr LZ9GG31 mother board lcd tv block diagram automatic WATER LEVEL pump CONTROL using ldr SA1111DEVMOD SA-1110 fpga based fire alarm system block diagram
Text: Intel StrongARM* SA-1110 Microprocessor Development Board User’s Guide June 2000 Hardware Build Phase 5 Order Number: 278278-006 Information in this document is provided in connection with Intel® products. No license, express or implied, by estoppel or otherwise, to any intellectual
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SA-1110
SA-1110
speed control of dc motor using scr mini project
AUTOMATIC ROOM LIGHT CONTROLLER using ldr
LED TV Screen working Theory
AUTOMATIC ROOM LIGHT generator using ldr
LZ9GG31
mother board lcd tv block diagram
automatic WATER LEVEL pump CONTROL using ldr
SA1111DEVMOD
fpga based fire alarm system block diagram
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Intel 8081
Abstract: 8051 Read Write for 80c188 80C188 I960 XRT82L24A XRT82L24AIV encoder line driver
Text: áç XRT82L24A QUAD E1 LINE TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR AUGUST 2004 REV. 1.1.2 GENERAL DESCRIPTION • Per-channel transmit power shutdown The XRT82L24A is a fully integrated Quad four channels short-haul line interface unit for E1(2.048Mbps)
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XRT82L24A
XRT82L24A
048Mbps)
Intel 8081
8051 Read Write for 80c188
80C188
I960
XRT82L24AIV
encoder line driver
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rur 450
Abstract: Intel 8081
Text: áç XRT82L24 QUAD E1 LINE TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR MARCH 2003 REV. 1.2.3 GENERAL DESCRIPTION • High receiver interference immunity The XRT82L24 is a fully integrated Quad four channels short-haul line interface unit for E1(2.048Mbps)
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XRT82L24
XRT82L24
048Mbps)
rur 450
Intel 8081
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intel 80c188 users manual
Abstract: i906
Text: áç XRT82L24 QUAD E1 LINE TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR APRIL 2001 REV. 1.1.0 GENERAL DESCRIPTION • High receiver interference immunity The XRT82L24 is a fully integrated Quad four channels short-haul line interface unit for E1(2.048Mbps)
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XRT82L24
XRT82L24
048Mbps)
intel 80c188 users manual
i906
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8192KB
Abstract: STLC5460 AD-018 DIP40 PLCC44 ST5421 ST5451 STLC3040 STLC5411 AD-016
Text: STLC5460 LINE CARD INTERFACE CONTROLLER PRODUCT PREVIEW DIP40 PLCC44 ORDERING NUMBER: STLC5460 PIN CONNECTIONS Top views VDD 1 40 RES RxD3 2 39 VSS2 RxD2 3 38 P1 RxD1 4 37 DOUT0 RxD0 5 36 DOUT1 TSC0 6 35 DIN0 TxD0 7 34 DIN1 TSC1 8 33 VDD2 TxD1 9 32 P0 TSC2
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STLC5460
DIP40
PLCC44
8192KB
STLC5460
AD-018
DIP40
PLCC44
ST5421
ST5451
STLC3040
STLC5411
AD-016
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prbs pattern generator
Abstract: 7seg5 XRT83VSH28 XRT83VSH28IB
Text: XRT83VSH28 PRELIMINARY 8-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT AUGUST 2006 REV. P1.0.0 GENERAL DESCRIPTION The on-chip clock synthesizer generates an E1 clock reference. The XRT83VSH28 is a fully integrated 8-channel short-haul line interface unit LIU that operates from
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XRT83VSH28
XRT83VSH28
prbs pattern generator
7seg5
XRT83VSH28IB
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Untitled
Abstract: No abstract text available
Text: XRT83VSH28 8-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT SEPTEMBER 2007 REV. 1.0.0 GENERAL DESCRIPTION The on-chip clock synthesizer generates an E1 clock reference. The XRT83VSH28 is a fully integrated 8-channel short-haul line interface unit LIU that operates from
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XRT83VSH28
XRT83VSH28
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MCP860
Abstract: T26 ferrite MPC86X XRT83VSH28 XRT83VSH28IB 8051 intel dmo2 0x81h
Text: XRT83VSH28 8-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT MARCH 2010 REV. 2.0.0 GENERAL DESCRIPTION The on-chip clock synthesizer generates an E1 clock reference. The XRT83VSH28 is a fully integrated 8-channel short-haul line interface unit LIU that operates from
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XRT83VSH28
XRT83VSH28
MCP860
T26 ferrite
MPC86X
XRT83VSH28IB
8051 intel
dmo2
0x81h
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CD 2399 GP
Abstract: No abstract text available
Text: INTEL CORP U P/ PR PH LS b?E D • Hfl2bl75 D l S 7 3 b tî SEI « I T L 1 in t e i Intel486 DX MICROPROCESSOR ■ Binary Com patible with Large Softw are Base -M S - D O S * , O S /2 *, W indows* — U N IX * System V /3 8 6 — iRMX , iRMK Kernels
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Hfl2bl75
Intel486â
168-Pin
32-Bit
4c00h
CD 2399 GP
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Untitled
Abstract: No abstract text available
Text: DATA SH EET JANUARY 1999 Revision 2.0 LXP730 Multi-Rate DSL Framer General Description The LXP730 is a multi-purpose Digital Subscriber Line DSL framer which complements the Level One SK70725/21 Enhanced MDSL Data Pump (EMDP) to provide seamless transport of data and voice signals over
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LXP730
LXP730
SK70725/21
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Intel 8081
Abstract: intel 80c188 users manual rur 450
Text: áç XRT82L24A QUAD E1 LINE TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR AUGUST 2004 REV. 1.1.2 GENERAL DESCRIPTION • Per-channel transmit power shutdown The XRT82L24A is a fully integrated Quad four channels short-haul line interface unit for E1(2.048Mbps)
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XRT82L24A
XRT82L24A
048Mbps)
31-Jul-09
XRT82L24AIV-F
LQFP100
XRT82L24AIV
LQFP100
Intel 8081
intel 80c188 users manual
rur 450
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AU-AIS
Abstract: SDH 209 E001 IXF6012 IXF6048 55236 GCIXF6012E w213 marking tuifdp marking f25 ku
Text: Intel IXF6012 51/155/622 Mbit/s SONET/SDH Cell/Packet Interface Datasheet Intel® IXF6012 is a single-chip interface solution for the transport of ATM cells or HDLC frames over SONET/SDH. Intel® IXF6012 can operate as a quad 51/155 Mbit/s or as a single
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IXF6012
IXF6012
AU-AIS
SDH 209
E001
IXF6048
55236
GCIXF6012E
w213 marking
tuifdp
marking f25 ku
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dtc12
Abstract: No abstract text available
Text: DATA SHEET JUNE 1999 Revision 2.0 LXT6251 21 E1 SDH Mapper General Description Features The LXT6251 21E1 Mapper performs asynchronous mapping and demapping of 21 E l PDH signals into SDH. The PDH side interfaces with E l LIUs and framers via NRZ Clock & Data, while the SDH side uses a standard
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LXT6251
LXT6251
LXT6051
VC-12
dtc12
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ntc 47d
Abstract: ti75b NTC 4.7d -7 BIG IP F5 D30 ntc 5 om d21 ufc 101 vc
Text: MB86683B Edition 2.0 1. OVERVIEW The NTC is a full duplex device which can be used to provide broadband term ination functions in a variety of applications. Its primary use is for term inating the user or network ends of a user-netw ork interface based on ITU-T,
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MB86683B
MB86686A/7)
ntc 47d
ti75b
NTC 4.7d -7
BIG IP F5 D30
ntc 5 om d21
ufc 101 vc
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