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    729-Pin

    Abstract: Axcelerator FPGAs AX125 IO126PB3F11 AG18 FBGA 896 896-Pin Axcelerator Family FPGAs
    Text: Axcelerator Family FPGAs Package Pin Assignments 180-Pin CSP A1 Ball Pad Corner 14 13 12 11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L M N P Figure 3-1 • 180-Pin CSP Bottom View Note For Package Manufacturing and Environmental information, visit Resource center at


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    PDF 180-Pin AX125 IO32NB3F3 IO59NB5F5 729-Pin Axcelerator FPGAs IO126PB3F11 AG18 FBGA 896 896-Pin Axcelerator Family FPGAs

    LGA 478 SOCKET PIN LAYOUT

    Abstract: RTAX2000
    Text: v5.2 RTAX-S/SL RadTolerant FPGAs Radiation Performance Leading-Edge Performance • • • • • • • • • • SEU-Hardened Registers Eliminate the Need for TripleModule Redundancy TMR – Immune to Single-Event Upsets (SEU) to LETTH > 37 MeV-cm2/mg


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    PDF TM1019 LGA 478 SOCKET PIN LAYOUT RTAX2000

    RTAX2000

    Abstract: footprint cqfp 280 RTAX1000S actel cqfp 84
    Text: A dv an c ed v0 .5 RTAX-S RadTolerant FPGAs Designed for Space • • • • • • • • SEU-Hardened Registers Eliminate the Need for Triple-Module Redundancy TMR – Immune to Single-Event Upsets (SEU) to LETth > 60 MeV-cm2/mg – SEU Rate < 10-10 Errors/Bit-Day in Worst-Case


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    PDF TM1019 RTAX2000 footprint cqfp 280 RTAX1000S actel cqfp 84

    56 pin edac connector

    Abstract: PCB footprint cqfp 132 Silicon Sculptor II ACTEL CCGA 624 mechanical
    Text: v2.0 RTAX-S RadTolerant FPGAs Designed for Space • • • • • • • • SEU-Hardened Registers Eliminate the Need for Triple-Module Redundancy TMR – Immune to Single-Event Upsets (SEU) to LETTH > 37 MeV-cm2/mg – SEU Rate < 10-10 Errors/Bit-Day in Worst-Case


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    PDF TM1019 56 pin edac connector PCB footprint cqfp 132 Silicon Sculptor II ACTEL CCGA 624 mechanical

    RTAX2000

    Abstract: rtax4000 CDB 455 C34 IO358 DIODE SMD V05 128X3
    Text: v5.1 RTAX-S/SL RadTolerant FPGAs Radiation Performance Leading-Edge Performance • • • • • • • • • • SEU-Hardened Registers Eliminate the Need for TripleModule Redundancy TMR – Immune to Single-Event Upsets (SEU) to LETTH > 37 MeV-cm2/mg


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    PDF TM1019 RTAX2000 rtax4000 CDB 455 C34 IO358 DIODE SMD V05 128X3

    ACTEL CCGA 1152 mechanical

    Abstract: AX125 AX2000 CQ208 CQ256 CS180 FG256 PQ208 Trd16 Axcelerator Family FPGAs
    Text: v2.8 Axcelerator Family FPGAs u e Leading-Edge Performance • • • • – 350+ MHz System Performance 500+ MHz Internal Performance High-Performance Embedded FIFOs 700 Mb/s LVDS Capable I/Os Specifications • • • • • Up to 2 Million Equivalent System Gates


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    dunlop s 708

    Abstract: PTI 30 040 ga AX125 AX2000 CS180 FG256 FG324 FG484 PQ208 M33 thermal fuse
    Text: Advanced v1.5  Axcelerator Family FPGAs Le adi n g- E dg e P e rfo r ma nc e • • • • – Voltage-Referenced I/O Standards: GTL+, HSTL Class 1, SSTL2 Class 1 and 2, SSTL3 Class 1 and 2 – Registered I/Os with 64-bit Deep FIFO on Each Pin "PerPin FIFO"


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    PDF 64-bit 608-bit dunlop s 708 PTI 30 040 ga AX125 AX2000 CS180 FG256 FG324 FG484 PQ208 M33 thermal fuse

    Untitled

    Abstract: No abstract text available
    Text: Revision 16 RTAX-S/SL and RTAX-DSP Radiation-Tolerant FPGAs Radiation Performance Specifications • SEU-Hardened Registers Eliminate the Need for Triple-Module Redundancy TMR – Immune to Single-Event Upsets (SEU) to LETTH > 37 MeVcm2/mg – SEU Rate < 10-10 Errors/Bit-Day (worst case GEO)


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    PDF TM1019 MIL-STD-883B

    ACTEL CCGA 1152 mechanical

    Abstract: lga 4x4 footprint AX125 AX2000 CQ208 CS180 FG256 PQ208 624-Pin tx 434
    Text: v2.7 Axcelerator Family FPGAs u e Leading-Edge Performance • • • • – 350+ MHz System Performance 500+ MHz Internal Performance High-Performance Embedded FIFOs 700 Mb/s LVDS Capable I/Os Specifications • • • • • Up to 2 Million Equivalent System Gates


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    56 pin edac connector

    Abstract: RTAX1000 edac 96 pin edac connector 292 CCGA
    Text: v2.1 RTAX-S RadTolerant FPGAs Designed for Space • • • • • • • • SEU-Hardened Registers Eliminate the Need for Triple-Module Redundancy TMR – Immune to Single-Event Upsets (SEU) to LETTH > 37 MeV-cm2/mg – SEU Rate < 10-10 Errors/Bit-Day in Worst-Case


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    PDF TM1019 56 pin edac connector RTAX1000 edac 96 pin edac connector 292 CCGA

    DP U1

    Abstract: IO317 AX1000
    Text: Advanced v1.5  Axcelerator Family FPGAs Leading-Edge Performance • • • • – Voltage-Referenced I/O Standards: GTL+, HSTL Class 1, SSTL2 Class 1 and 2, SSTL3 Class 1 and 2 – Registered I/Os with 64-bit Deep FIFO on Each Pin "PerPin FIFO" – Hot-Swap Compliant I/Os (Except PCI)


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    PDF 700Mb/s 339kbits DP U1 IO317 AX1000

    GCLR

    Abstract: 676P Axcelerator Family FPGAs
    Text: v2.4 Axcelerator Family FPGAs u e Leading-Edge Performance • • • • – 350+ MHz System Performance 500+ MHz Internal Performance High-Performance Embedded FIFOs 700 Mb/s LVDS Capable I/Os Specifications • • • • • Up to 2 Million Equivalent System Gates


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    AF4 din 74

    Abstract: AF2.5 din 74 diode t25 4 g8 Axcelerator Family FPGAs
    Text: v2.5 Axcelerator Family FPGAs u e Leading-Edge Performance • • • • – 350+ MHz System Performance 500+ MHz Internal Performance High-Performance Embedded FIFOs 700 Mb/s LVDS Capable I/Os Specifications • • • • • Up to 2 Million Equivalent System Gates


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    4x1K

    Abstract: edac 96 pin edac connector footprint cqfp 132 833 T12
    Text: Advanced v0.5 RTAX-S RadTolerant FPGAs Designed for Space • • • • • • • • SEU-Hardened Registers Eliminate the Need for Triple-Module Redundancy TMR – Immune to Single-Event Upsets (SEU) to LETth > 60 MeV-cm2/mg – SEU Rate < 10-10 Errors/Bit-Day in Worst-Case


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    PDF TM1019 4x1K edac 96 pin edac connector footprint cqfp 132 833 T12

    RTAX2000

    Abstract: RTAX2000S RTAX1000SL rtax250 RTAX250SL RTAX4000SL RTAX1000 RTAX-S RTAX1000S-SL rtax250s
    Text: Rev ision 13 RTAX-S/SL and RTAX-DSP Radiation-Tolerant FPGAs Radiation Performance Specifications • SEU-Hardened Registers Eliminate the Need for Triple-Module Redundancy TMR – Immune to Single-Event Upsets (SEU) to LETTH > 37 MeVcm2/mg – SEU Rate < 10-10 Errors/Bit-Day (worst case GEO)


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    PDF TM1019 MIL-STD-883B Extended600 RTAX2000 RTAX2000S RTAX1000SL rtax250 RTAX250SL RTAX4000SL RTAX1000 RTAX-S RTAX1000S-SL rtax250s

    Axcelerator FPGAs

    Abstract: AX125 AX2000 CQ208 CS180 PQ208 M33 thermal fuse AK 1022 Axcelerator Family FPGAs
    Text: v2 .1  Axcelerator Family FPGAs u e Leading-Edge Performance • • • • – 350+ MHz System Performance 500+ MHz Internal Performance High-Performance Embedded FIFOs 700Mb/s LVDS Capable I/Os Specifications • • • • • Up to 2 Million Equivalent System Gates


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    PDF 700Mb/s 295kbits Axcelerator FPGAs AX125 AX2000 CQ208 CS180 PQ208 M33 thermal fuse AK 1022 Axcelerator Family FPGAs

    ACTEL CCGA 1152 mechanical

    Abstract: ACTEL CCGA 624 mechanical L33 thermal fuse ACTEL CCGA 1152 pin configuration actel PLL schematic footprint cqfp 240 m20 thermal fuse 115 M33 thermal fuse AX125 AX2000
    Text: v2.6 Axcelerator Family FPGAs u e Leading-Edge Performance • • • • – 350+ MHz System Performance 500+ MHz Internal Performance High-Performance Embedded FIFOs 700 Mb/s LVDS Capable I/Os Specifications • • • • • Up to 2 Million Equivalent System Gates


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    b h21

    Abstract: No abstract text available
    Text: Revision 18 Axcelerator Family FPGAs Leading-Edge Performance • • • • 350+ MHz System Performance 500+ MHz Internal Performance High-Performance Embedded FIFOs 700 Mb/s LVDS Capable I/Os Specifications • • • • • Up to 2 Million Equivalent System Gates


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    PDF 608-bit b h21

    AX1000

    Abstract: No abstract text available
    Text: Advanced v1.3  Axcelerator Family FPGAs Leading-Edge Performance • • • • – Voltage-Referenced I/O Standards: GTL+, HSTL Class 1, SSTL2 Class 1 and 2, SSTL3 Class 1 and 2 – Registered I/Os with 64-bit Deep FIFO on Each Pin "PerPin FIFO" – Hot-Swap Compliant I/Os (Except PCI)


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    PDF 64-bit 608-bit 14tains AX1000

    w32 smd transistor

    Abstract: rtax250sl RTAX2000S w32 smd transistor 143 41-bit Carry Look-ahead Adder RTAX2000SL RTAX4000S BY415 RTAX4000D LG1152
    Text: Revision 14 RTAX-S/SL and RTAX-DSP Radiation-Tolerant FPGAs Radiation Performance Specifications • SEU-Hardened Registers Eliminate the Need for Triple-Module Redundancy TMR – Immune to Single-Event Upsets (SEU) to LETTH > 37 MeVcm2/mg – SEU Rate < 10-10 Errors/Bit-Day (worst case GEO)


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    PDF TM1019 MIL-STD-883B w32 smd transistor rtax250sl RTAX2000S w32 smd transistor 143 41-bit Carry Look-ahead Adder RTAX2000SL RTAX4000S BY415 RTAX4000D LG1152

    AX125

    Abstract: AX2000 CQ208 CQ256 FG256 FG324 PQ208 AX2000-CQ256
    Text: Revision 17 Axcelerator Family FPGAs Leading-Edge Performance • • • • 350+ MHz System Performance 500+ MHz Internal Performance High-Performance Embedded FIFOs 700 Mb/s LVDS Capable I/Os Specifications • • • • • Up to 2 Million Equivalent System Gates


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    AF367

    Abstract: AK 1022 IC KA 2312 P2272 AX1000
    Text: Advanced v1.6  Axcelerator Family FPGAs Le adi n g- E dg e P e rfo r ma nc e • • • • 350+ MHz System Performance 500+ MHZ Internal Performance High-Performance Embedded FIFOs 700Mb/s LVDS Capable I/Os S pe ci fi c at i on s • • • • • Up to 2 Million Equivalent System Gates


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    PDF 700Mb/s 295kbits AF367 AK 1022 IC KA 2312 P2272 AX1000

    CQ352-FPGA

    Abstract: RTAX1000s-cq RTAX4000S RTAX2000 RTAX2000S-CQ352 FPGA Application Note schematic 324 CDB 455 C34 rtax4000 AP3433
    Text: v4.0 RTAX-S RadTolerant FPGAs Designed for Space • • • • • • • SEU-Hardened Registers Eliminate the Need for Triple-Module Redundancy TMR – Immune to Single-Event Upsets (SEU) to LETTH > 37 MeV-cm2/mg – SEU Rate < 10-10 Errors/Bit-Day in Worst-Case


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    PDF TM1019 CQ352-FPGA RTAX1000s-cq RTAX4000S RTAX2000 RTAX2000S-CQ352 FPGA Application Note schematic 324 CDB 455 C34 rtax4000 AP3433

    IO191

    Abstract: Axcelerator Family FPGAs
    Text: v2.3 Axcelerator Family FPGAs u e Leading-Edge Performance • • • • – 350+ MHz System Performance 500+ MHz Internal Performance High-Performance Embedded FIFOs 700 Mb/s LVDS Capable I/Os Specifications • • • • • Up to 2 Million Equivalent System Gates


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