ISSI Signs SRAM Technology Licensing Agreement with IBM

Abstract: Licensing Agreement with IBM
Contextual Info: ISSI Signs SRAM Technology Licensing Agreement with IBM SAN JOSE, Calif., Feb. 27, 2012 - ISSI has signed a technology licensing agreement with IBM around SRAM technology, enhancing a relationship that started in 2004 for SRAM technology. Said Tom Reeves, VP of Business Development and Licensing, at IBM: "IBM has a rich and extensive IP portfolio in

Samsung EOL

Abstract: IS42S81600F is42s16320 IS43DR16320 IS42S32200L IS49NLC36800 IS43R32400E IS46R Mobile SDRAM IS42S32200E
Contextual Info: Industrial Grade Memory Products Selecting the Right ISSI Industrial Grade Memory Fastest Random Access Access <20ns 288-576Mb Memory No DRC* Lower cost/bit 18-72Mb RLDRAM 10-20ns Easy Interface, Low Power Higher Density Ultra Low Power Synch SRAM <5ns Asynch SRAM

is62c51216al

Abstract: IS43LR16320B IS66WVE4M16BLL is66wve2m16 IS43DR16640A BGA60 IS66WVE4M16ALL TSOP2-44 IS42SM16400G is45vs16160d
Contextual Info: To our valued customers, At ISSI we design, develop and market high performance integrated circuits for the following key markets: i automotive electronics (ii) networking/telecommunications infrastructure, (iii) industrial/military/medical electronics (iv) mobile communications and digital

Contextual Info: IS61LSSDH51236 IS61LSSDH102418 ISSI ΣQUAD 18Mb Σ2x2B2 ADVANCE INFORMATION DECEMBER 2002 DDR SEPERATE I/O SRAM FEATURES • Simultaneous Read and Write SigmaQuad Interface • SigmaRAM™ JEDEC standard pinout/package • Dual Double Data Rate interface

Contextual Info: ISSI IS61LSSS51236, IS61LSSS102418 ΣQUAD 18Mb Σ2x1B2 ADVANCE INFORMATION DECEMBER 2002 SDR SEPERATE I/O SRAM FEATURES • Simultaneous Read and Write SigmaQuad Interface • Dual Single Data Rate interface • Echo Clock outputs track data output drivers

Contextual Info: ISSI IS61LSSS51236, IS61LSSS102418 ΣQUAD 18Mb Σ2x1B2 ADVANCE INFORMATION JUNE 2002 SDR SEPARATE I/O SRAM FEATURES • Simulatneous Read and Write SigmaQuad Interface • Dual Single Data Rate interface • Echo Clock outputs track data output drivers

Contextual Info: ISSI IS61LSSD102418 ΣQUAD 18Mb Σ2x2B4 ADVANCE INFORMATION DECEMBER 2002 DDR SEPARATE I/O SRAM FEATURES • Simultaneous Read and Write SigmaQuad Interface • JEDEC standard pinout and package • Dual Double Data Rate interface • Echo Clock outputs track data output drivers

Contextual Info: ISSI IS61LSSD102418 ΣQUAD 18Mb Σ2x2B4 ADVANCE INFORMATION JUNE 2002 DDR SEPARATE I/O SRAM FEATURES • Simulatneous Read and Write SigmaQuad Interface • JEDEC standard pinout and package • Dual Double Data Rate interface • Echo Clock outputs track data output drivers

Contextual Info: IS61LSSDH51236 IS61LSSDH102418 ISSI SQUAD 18Mb S2x2B2 ADVANCE INFORMATION JUNE 2002 DDR SEPERATE I/O SRAM FEATURES • Simultaneous Read and Write SigmaQuad Interface • SigmaRAM™ JEDEC standard pinout/package • Dual Double Data Rate interface • Echo Clock outputs track data output drivers

16M X 32 SDR SDRAM

Abstract: IS42VM16400K is66wve2m16 IS42SM16100G is66wvc4m16 ISSI IS42S16400j IS66WVC4M16ALL CRAM 256mb IS42RM16800G
Contextual Info: Known Good Die KGD /Wafer Level Memories Introduction Die-level customers require a memory partner who can meet their many unique needs for high quality, long term support, guaranteed availability, and low total cost of ownership. ISSI is a provider of high quality specialty memory solutions for

Contextual Info: 36 Mb 1M x 36 & 2M x 18 QUAD (Burst of 2) Synchronous SRAMs . ISSI OCTOBER 2006 Features • 1M x 36 or 2M x 18. • On-chip delay-locked loop (DLL) for wide data valid window. • Separate read and write ports with concurrent read and write operations.

Contextual Info: 36 Mb 1M x 36 & 2M x 18 QUAD (Burst of 4) Synchronous SRAMs . ISSI April 2005 Features • 1M x 36 or 2M x 18. • On-chip delay-locked loop (DLL) for wide data valid window. • Separate read and write ports with concurrent read and write operations.

D0-35

Abstract: IS61QDB21M36-250M3 IS61QDB21M36-250M3L
Contextual Info: 36 Mb 1M x 36 & 2M x 18 QUAD (Burst of 2) Synchronous SRAMs . ISSI JULY 2006 Features • 1M x 36 or 2M x 18. • On-chip delay-locked loop (DLL) for wide data valid window. • Separate read and write ports with concurrent read and write operations.

Contextual Info: 36 Mb 1M x 36 & 2M x 18 QUAD (Burst of 2) Synchronous SRAMs . ISSI February 2005 Features • 1M x 36 or 2M x 18. • On-chip delay-locked loop (DLL) for wide data valid window. • Separate read and write ports with concurrent read and write operations.

IS43LR32640

Abstract: is61wv5128 Product Selector Guide is42s86400 IS46R16160B IS25LD010 IS25LD025 IS25LQ IS62WV5128DALL BGA 168
Contextual Info: To our valued customers, At ISSI we design, develop and market high performance integrated circuits for the following key markets: i automotive, (ii) communications, (iii) digital consumer, and (iv) industrial/medical/military. These key markets all require high quality and reliability, extended temperature ranges, and long-term support. Our primary products are high speed and

IS61DDB21M36

Abstract: IS61DDB22M18
Contextual Info: 36 Mb 1M x 36 & 2M x 18 DDR-II (Burst of 2) CIO Synchronous SRAMs . ISSI May 2005 Features • 1M x 36 or 2M x 18. • On-chip delay-locked loop (DLL) for wide data valid window. • Common data input/output bus. • Synchronous pipeline read with self-timed late

ISSI

Abstract: DDR-3
Contextual Info: ► DRAM PRODUCT LINE Strategy: Provide complete portfolio of low-to-medium density and low power DRAMs • Long-term support for all ISSI DRAMs: 7-10 years typical • SDRAM in all densities up to 512Mb, including x32 products SDR, DDR, DDR2 • Mobile DRAMs for SDR and DDR families for power sensitive application

Contextual Info: 36 Mb 1M x 36 & 2M x 18 DDR-II (Burst of 2) CIO Synchronous SRAMs . ISSI March 2005 Features • 1M x 36 or 2M x 18. • On-chip delay-locked loop (DLL) for wide data valid window. • Common data input/output bus. • Synchronous pipeline read with self-timed late

Contextual Info: 36 Mb 1M x 36 & 2M x 18 DDR-II (Burst of 4) CIO Synchronous SRAMs . ISSI July 2007 Features • 1M x 36 or 2M x 18. • On-chip delay-locked loop (DLL) for wide data valid window. • Common I/O read and write ports. • Synchronous pipeline read with late write operation.

Contextual Info: 36 Mb 1M x 36 & 2M x 18 DDR-II (Burst of 4) CIO Synchronous SRAMs . ISSI March 2005 Features • 1M x 36 or 2M x 18. • On-chip delay-locked loop (DLL) for wide data valid window. • Common I/O read and write ports. • Synchronous pipeline read with late write operation.

d917

Abstract: IS61DDB41M36 IS61DDB42M18
Contextual Info: 36 Mb 1M x 36 & 2M x 18 DDR-II (Burst of 4) CIO Synchronous SRAMs . ISSI May 2005 Features • 1M x 36 or 2M x 18. • On-chip delay-locked loop (DLL) for wide data valid window. • Common I/O read and write ports. • Synchronous pipeline read with late write operation.

IS61QDB41M36-200M3

Abstract: IS61QDB42M18 IS61QDB42M18-200M3 D0-35 IS61QDB41M36 2M x 18
Contextual Info: 36 Mb 1M x 36 & 2M x 18 QUAD (Burst of 4) Synchronous SRAMs . ISSI May 2005 Features • 1M x 36 or 2M x 18. • On-chip delay-locked loop (DLL) for wide data valid window. • Separate read and write ports with concurrent read and write operations. • Synchronous pipeline read with late write operation.

Contextual Info: 36 Mb 1M x 36 & 2M x 18 QUAD (Burst of 4) Synchronous SRAMs . I March 2008 Features • 1M x 36 or 2M x 18. • On-chip delay-locked loop (DLL) for wide data valid window. • Separate read and write ports with concurrent read and write operations. • Synchronous pipeline read with late write operation.

2M x 18

Contextual Info: 36 Mb 1M x 36 & 2M x 18 QUAD (Burst of 4) Synchronous SRAMs . I January 2009 Features • 1M x 36 or 2M x 18. • On-chip delay-locked loop (DLL) for wide data valid window. • Separate read and write ports with concurrent read and write operations. • Synchronous pipeline read with late write operation.