SC2597SETRC
Abstract: No abstract text available
Text: SC2597 Low Voltage DDR Termination Regulator POWER MANAGEMENT Features Description The SC2597 is designed to meet the latest JEDEC specification for low power DDR3 and DDR4, while also supporting DDR and DDR2. The SC2597 regulates up to + 3A for VTT and up to + 40mA for VREF.
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SC2597
SC2597
SC2597SETRC
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DDR4 pcb layout guidelines
Abstract: DDR4 jedec EV1320 JEDEC DDR4 pcb layout EV1320QI DDR4 "application note" EV1320QI-E
Text: EV1320QI 2A Source/Sink DDR Memory Termination Converter Description Features The EV1320QI is a DC to DC converter specifically designed for memory termination applications. The device offers high efficiency, up to 96%, while providing a solution footprint similar to that of a linear
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EV1320QI
16-pin
DDR4 pcb layout guidelines
DDR4 jedec
EV1320
JEDEC DDR4 pcb layout
DDR4 "application note"
EV1320QI-E
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DDR4 pcb layout guidelines
Abstract: EV1320QI
Text: Enpirion Power Datasheet EV1320QI 2A PowerSoC Source/Sink DDR Memory Termination Converter Description Features The EV1320QI is a DC to DC converter specifically designed for memory termination applications. The device offers high efficiency, up to 96%, while
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EV1320QI
16-pin
DDR4 pcb layout guidelines
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QSFP28 I2C
Abstract: No abstract text available
Text: Arria 10 Device Overview 2013.09.04 AIB-01023 Subscribe Feedback Altera’s Arria FPGAs and SoCs deliver optimal performance and power efficiency in the midrange. By using TSMC's 20-nm process technology on a high-performance architecture, Arria 10 FPGAs and SoCs
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AIB-01023
20-nm
QSFP28 I2C
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DDR3 pcb layout guide
Abstract: ddr3 ram DDR4 TPS51200DRCR SON-10 TPS51100 TPS51200 TPS51200DRCT UDG-08034 DDR3 layout TI
Text: TPS51200 www.ti.com SLUS812 – FEBRUARY 2008 SINK/SOURCE DDR TERMINATION REGULATOR FEATURES APPLICATIONS • Input Voltage: Supports 2.5-V Rail and 3.3-V Rail • VLDOIN Voltage Range: 1.1 V to 3.5 V • Sink/Source Termination Regulator Includes Droop Compensation
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TPS51200
SLUS812
10-mA
DDR3 pcb layout guide
ddr3 ram
DDR4
TPS51200DRCR
SON-10
TPS51100
TPS51200
TPS51200DRCT
UDG-08034
DDR3 layout TI
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JEDEC DDR4 pcb layout
Abstract: DDR4 pcb layout guidelines
Text: TPS51200-Q1 www.ti.com SLUS984 – NOVEMBER 2009 SINK/SOURCE DDR TERMINATION REGULATOR Check for Samples: TPS51200-Q1 FEATURES APPLICATIONS • • • 1 2 • • • • • • • • • • • • Qualified for Automotive Applications Input Voltage: Supports 2.5-V Rail and 3.3-V
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TPS51200-Q1
SLUS984
10-mA
JEDEC DDR4 pcb layout
DDR4 pcb layout guidelines
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Untitled
Abstract: No abstract text available
Text: TPS51200 w w w .t i.c om SLUS812 – FEBRUARY 2008 SINK/SOURCE DDR TERMINATION REGULATOR FEATURES APPLICATIONS • Input Voltage: Supports 2.5-V Rail and 3.3-V Rail • VLDOIN Voltage Range: 1.1 V to 3.5 V • Sink/Source Termination Regulator Includes Droop Compensation
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TPS51200
SLUS812
10-mA
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Untitled
Abstract: No abstract text available
Text: TPS51200 www.ti.com SLUS812 – FEBRUARY 2008 SINK/SOURCE DDR TERMINATION REGULATOR FEATURES APPLICATIONS • Input Voltage: Supports 2.5-V Rail and 3.3-V Rail • VLDOIN Voltage Range: 1.1 V to 3.5 V • Sink/Source Termination Regulator Includes Droop Compensation
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TPS51200
SLUS812
10-mA
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Untitled
Abstract: No abstract text available
Text: TPS51200-Q1 www.ti.com SLUS984 – NOVEMBER 2009 SINK/SOURCE DDR TERMINATION REGULATOR Check for Samples: TPS51200-Q1 FEATURES APPLICATIONS • • • 1 2 • • • • • • • • • • • • Qualified for Automotive Applications Input Voltage: Supports 2.5-V Rail and 3.3-V
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TPS51200-Q1
SLUS984
10-mA
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DDR4 pcb layout guidelines
Abstract: DDR3 pcb layout motherboard DDR3 pcb layout DIMM DDR4 socket pcb layout design mobile DDR DDR4 DIMM SPD JEDEC DDR4 jedec
Text: TPS51200 www.ti.com SLUS812 – FEBRUARY 2008 SINK/SOURCE DDR TERMINATION REGULATOR FEATURES APPLICATIONS • Input Voltage: Supports 2.5-V Rail and 3.3-V Rail • VLDOIN Voltage Range: 1.1 V to 3.5 V • Sink/Source Termination Regulator Includes Droop Compensation
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TPS51200
SLUS812
10-mA
DDR4 pcb layout guidelines
DDR3 pcb layout motherboard
DDR3 pcb layout
DIMM DDR4 socket
pcb layout design mobile DDR
DDR4 DIMM SPD JEDEC
DDR4 jedec
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DDR3 pcb layout motherboard
Abstract: DDR3 pcb layout guide DDR4 pcb layout guidelines DDR3 pcb layout TPS51200-Q1 DDR3 pcb layout guidelines lpddr3 TPS51200-EVM
Text: TPS51200-Q1 www.ti.com SLUS984A – NOVEMBER 2009 – REVISED APRIL 2012 SINK/SOURCE DDR TERMINATION REGULATOR Check for Samples: TPS51200-Q1 FEATURES APPLICATIONS • • • 1 2 • • • • • • • • • • • • Qualified for Automotive Applications
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TPS51200-Q1
SLUS984A
10-mA
DDR3 pcb layout motherboard
DDR3 pcb layout guide
DDR4 pcb layout guidelines
DDR3 pcb layout
TPS51200-Q1
DDR3 pcb layout guidelines
lpddr3
TPS51200-EVM
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DDR4 pcb layout guidelines
Abstract: DDR4 DIMM SPD JEDEC TPS51200QDRCRQ1 ddr3 ram MURATA MW 20 Top side device marking of TPS51200 SON-10 TPS51100 TPS51200 tps51100 marking
Text: TPS51200-Q1 www.ti.com SLUS984 – NOVEMBER 2009 SINK/SOURCE DDR TERMINATION REGULATOR Check for Samples: TPS51200-Q1 FEATURES APPLICATIONS • • • 1 2 • • • • • • • • • • • • Qualified for Automotive Applications Input Voltage: Supports 2.5-V Rail and 3.3-V
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TPS51200-Q1
SLUS984
10-mA
DDR4 pcb layout guidelines
DDR4 DIMM SPD JEDEC
TPS51200QDRCRQ1
ddr3 ram
MURATA MW 20
Top side device marking of TPS51200
SON-10
TPS51100
TPS51200
tps51100 marking
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DDR3 pcb layout guide
Abstract: ddr3 ram TPS51200DRCR SON-10 TPS51100 TPS51200 TPS51200DRCT DDR3 pcb layout
Text: TPS51200 www.ti.com SLUS812 – FEBRUARY 2008 SINK/SOURCE DDR TERMINATION REGULATOR FEATURES APPLICATIONS • Input Voltage: Supports 2.5-V Rail and 3.3-V Rail • VLDOIN Voltage Range: 1.1 V to 3.5 V • Sink/Source Termination Regulator Includes Droop Compensation
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TPS51200
SLUS812
10-mA
DDR3 pcb layout guide
ddr3 ram
TPS51200DRCR
SON-10
TPS51100
TPS51200
TPS51200DRCT
DDR3 pcb layout
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DDR4 pcb layout guidelines
Abstract: DDR3 pcb layout guide DDR3 pcb layout motherboard ddr3 pcb design guide TPS51200DRCT SON-10 TPS51100 TPS51200 TPS51200DRCR lpddr3
Text: TPS51200 www.ti.com SLUS812 – FEBRUARY 2008 SINK/SOURCE DDR TERMINATION REGULATOR FEATURES APPLICATIONS • Input Voltage: Supports 2.5-V Rail and 3.3-V Rail • VLDOIN Voltage Range: 1.1 V to 3.5 V • Sink/Source Termination Regulator Includes Droop Compensation
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TPS51200
SLUS812
10-mA
DDR4 pcb layout guidelines
DDR3 pcb layout guide
DDR3 pcb layout motherboard
ddr3 pcb design guide
TPS51200DRCT
SON-10
TPS51100
TPS51200
TPS51200DRCR
lpddr3
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SLUS984A
Abstract: No abstract text available
Text: TPS51200-Q1 www.ti.com SLUS984A – NOVEMBER 2009 – REVISED APRIL 2012 SINK/SOURCE DDR TERMINATION REGULATOR Check for Samples: TPS51200-Q1 FEATURES APPLICATIONS • • • 1 2 • • • • • • • • • • • • Qualified for Automotive Applications
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TPS51200-Q1
SLUS984A
10-mA
SLUS984A
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Untitled
Abstract: No abstract text available
Text: TPS51200 www.ti.com SLUS812 – FEBRUARY 2008 SINK/SOURCE DDR TERMINATION REGULATOR FEATURES APPLICATIONS • Input Voltage: Supports 2.5-V Rail and 3.3-V Rail • VLDOIN Voltage Range: 1.1 V to 3.5 V • Sink/Source Termination Regulator Includes Droop Compensation
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TPS51200
SLUS812
10-mA
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DDR4 pcb layout guidelines
Abstract: TPS51200DRCR JESD8-15a DDR4 jedec SON-10 TPS51100 TPS51200 TPS51200DRCT DDR3 pcb layout guide lpddr3
Text: TPS51200 www.ti.com SLUS812 – FEBRUARY 2008 SINK/SOURCE DDR TERMINATION REGULATOR FEATURES APPLICATIONS • Input Voltage: Supports 2.5-V Rail and 3.3-V Rail • VLDOIN Voltage Range: 1.1 V to 3.5 V • Sink/Source Termination Regulator Includes Droop Compensation
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TPS51200
SLUS812
10-mA
DDR4 pcb layout guidelines
TPS51200DRCR
JESD8-15a
DDR4 jedec
SON-10
TPS51100
TPS51200
TPS51200DRCT
DDR3 pcb layout guide
lpddr3
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TPS51200DRCR/2801
Abstract: No abstract text available
Text: TPS51200 www.ti.com SLUS812 – FEBRUARY 2008 SINK/SOURCE DDR TERMINATION REGULATOR FEATURES APPLICATIONS • Input Voltage: Supports 2.5-V Rail and 3.3-V Rail • VLDOIN Voltage Range: 1.1 V to 3.5 V • Sink/Source Termination Regulator Includes Droop Compensation
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TPS51200
SLUS812
10-mA
TPS51200DRCR/2801
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DDR3 layout
Abstract: DDR4 jedec
Text: TPS51200-Q1 www.ti.com SLUS984 – NOVEMBER 2009 SINK/SOURCE DDR TERMINATION REGULATOR Check for Samples: TPS51200-Q1 FEATURES APPLICATIONS • • • 1 2 • • • • • • • • • • • • Qualified for Automotive Applications Input Voltage: Supports 2.5-V Rail and 3.3-V
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TPS51200-Q1
SLUS984
10-mA
DDR3 layout
DDR4 jedec
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DDR4 pcb layout guidelines
Abstract: TPS51200-Q1 DDR4 "application note" DDR3 layout guidelines lpddr3 SLUS984A
Text: TPS51200-Q1 www.ti.com SLUS984A – NOVEMBER 2009 – REVISED APRIL 2012 SINK/SOURCE DDR TERMINATION REGULATOR Check for Samples: TPS51200-Q1 FEATURES APPLICATIONS • • • 1 2 • • • • • • • • • • • • Qualified for Automotive Applications
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TPS51200-Q1
SLUS984A
10-mA
DDR4 pcb layout guidelines
TPS51200-Q1
DDR4 "application note"
DDR3 layout guidelines
lpddr3
SLUS984A
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DDR4 pcb layout guidelines
Abstract: TPS51200-EVM DDR3 pcb layout motherboard DDR4 spd UDG-08023 JEDEC DDR4 pcb layout UDG-08034 DDR4 DIMM SPD JEDEC DDR4 jedec JESD8-15a
Text: TPS51200 www.ti.com SLUS812 – FEBRUARY 2008 SINK/SOURCE DDR TERMINATION REGULATOR FEATURES APPLICATIONS • Input Voltage: Supports 2.5-V Rail and 3.3-V Rail • VLDOIN Voltage Range: 1.1 V to 3.5 V • Sink/Source Termination Regulator Includes Droop Compensation
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TPS51200
SLUS812
10-mA
DDR4 pcb layout guidelines
TPS51200-EVM
DDR3 pcb layout motherboard
DDR4 spd
UDG-08023
JEDEC DDR4 pcb layout
UDG-08034
DDR4 DIMM SPD JEDEC
DDR4 jedec
JESD8-15a
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Untitled
Abstract: No abstract text available
Text: TPS51200-Q1 www.ti.com SLUS984A – NOVEMBER 2009 – REVISED APRIL 2012 SINK/SOURCE DDR TERMINATION REGULATOR Check for Samples: TPS51200-Q1 FEATURES APPLICATIONS • • • 1 2 • • • • • • • • • • • • Qualified for Automotive Applications
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TPS51200-Q1
SLUS984A
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DDR4 pcb layout guidelines
Abstract: DDR3 pcb layout guide tps51200drct RFID Tracking Pad 770 DDR3 pcb layout DDR3 pcb layout motherboard TPS51200-EVM DDR4 DIMM SPD JEDEC ddr3 pcb design guide DDR4
Text: TPS51200 www.ti.com SLUS812 – FEBRUARY 2008 SINK/SOURCE DDR TERMINATION REGULATOR FEATURES APPLICATIONS • Input Voltage: Supports 2.5-V Rail and 3.3-V Rail • VLDOIN Voltage Range: 1.1 V to 3.5 V • Sink/Source Termination Regulator Includes Droop Compensation
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TPS51200
SLUS812
10-mA
DDR4 pcb layout guidelines
DDR3 pcb layout guide
tps51200drct
RFID Tracking Pad 770
DDR3 pcb layout
DDR3 pcb layout motherboard
TPS51200-EVM
DDR4 DIMM SPD JEDEC
ddr3 pcb design guide
DDR4
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Untitled
Abstract: No abstract text available
Text: TPS51200-Q1 www.ti.com SLUS984A – NOVEMBER 2009 – REVISED APRIL 2012 SINK/SOURCE DDR TERMINATION REGULATOR Check for Samples: TPS51200-Q1 FEATURES APPLICATIONS • • • 1 2 • • • • • • • • • • • • Qualified for Automotive Applications
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TPS51200-Q1
SLUS984A
10-mA
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