SILEGO
Abstract: Silego Technology Q11A Q13A SLGSSTU32864 SLGSSTU32864E SLGSSTU32864EX SLGSSTU32864EX-TR SSTU32864 lfbga-96ball
Text: SLGSSTU32864E DDR2 Configurable Registered Buffer Applications: • PC3200/4300 DDR2 memory modules • 1:1 25-bit or 1:2 14-bit configurable registered buffer • 1.8V data registers Features: • Compatible with JEDEC standard SSTU32864 • Differential Clock inputs
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SLGSSTU32864E
PC3200/4300
25-bit
14-bit
SSTU32864
300MHz
SLGSSTU32864
SILEGO
Silego Technology
Q11A
Q13A
SLGSSTU32864E
SLGSSTU32864EX
SLGSSTU32864EX-TR
SSTU32864
lfbga-96ball
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PDF
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JC-42
Abstract: AAAC
Text: June 2004 ASM4SSTVF16857 rev 1.1 DDR 14-Bit Registered Buffer LVCMOS level at a valid logic state since VREF may Features • not be stable during power-up. Fully JEDEC JC40 - JC42.5 compliant for DDR1 applications to include: PC1600, PC2100, PC2700 & PC3200.
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14-Bit
ASM4SSTVF16857
PC1600,
PC2100,
PC2700
PC3200.
JC-42
AAAC
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PDF
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DDR DIMM pinout micron 184
Abstract: No abstract text available
Text: 128MB, 256MB x72, ECC , PC3200 184-Pin DDR SDRAM DIMM DDR SDRAM DIMM MT9VDDT1672A - 128MB MT9VDDT3272A - 256MB For the latest data sheet, please refer to the Micronâ Web site: www.micron.com/moduleds Features Figure 1: 184-Pin DIMM (MO-206) • JEDEC-standard 184-pin dual in-line memory
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128MB,
256MB
PC3200
184-Pin
PC3200A
128MB
09005aef80a43d77
DDA9C16
DDR DIMM pinout micron 184
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PDF
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Untitled
Abstract: No abstract text available
Text: 128MB, 256MB x72, ECC , PC3200 184-Pin DDR SDRAM DIMM DDR SDRAM DIMM MT9VDDT1672A - 128MB MT9VDDT3272A - 256MB For the latest data sheet, please refer to the Micronâ Web site: www.micron.com/moduleds Features Figure 1: 184-Pin DIMM (MO-206) • JEDEC-standard 184-pin dual in-line memory
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128MB,
256MB
PC3200
184-Pin
PC3200A
128MB
09005aef80a43d77
DDA9C16
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PDF
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Untitled
Abstract: No abstract text available
Text: 128MB, 256MB x72, ECC , PC3200A 184-Pin DDR SDRAM DIMM DDR SDRAM DIMM MT9VDDT1672A - 128MB MT9VDDT3272A - 256MB For the latest data sheet, please refer to the Micronâ Web site: www.micron.com/moduleds Features Figure 1: 184-Pin DIMM (MO-206) • JEDEC-standard 184-pin dual in-line memory
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Original
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128MB,
256MB
PC3200A
184-Pin
PC3200A
128MB
09005aef80a43d77
DDA9C16
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PDF
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NT256D64S88B1G-5T
Abstract: DDR400 DDR400A NT256D64S88B1G NT256D64S88B1G-5 PC3200
Text: NT256D64S88B1G-5 256MB : 32M x 64 PC3200 Unbuffered DDR DIMM 184pin Unbuffered DDR DIMM Based on DDR400 32Mx8 SDRAM Features • 32Mx64 Unbuffered DDR DIMM based on 32Mx8 DDR SDRAM • DRAM DLL aligns DQ and DQS transitions with clock transitions • JEDEC Standard 184-pin Dual In-Line Memory Module
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NT256D64S88B1G-5
256MB
PC3200
184pin
DDR400
32Mx8
32Mx64
184-pin
PC3200A
NT256D64S88B1G-5T
DDR400A
NT256D64S88B1G
NT256D64S88B1G-5
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PDF
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Untitled
Abstract: No abstract text available
Text: NT512D64S8HB1G-5 512MB : 64M x 64 PC3200A Unbuffered DDR DIMM 184pin Unbuffered DDR DIMM Based on DDR400A 32Mx8 SDRAM Features • 64Mx64 Unbuffered DDR DIMM based on 32Mx8 DDR SDRAM • DRAM DLL aligns DQ and DQS transitions with clock transitions • JEDEC Standard 184-pin Dual In-Line Memory Module
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NT512D64S8HB1G-5
512MB
PC3200A
184pin
DDR400A
32Mx8
64Mx64
184-pin
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PDF
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Untitled
Abstract: No abstract text available
Text: NT512D64S8HB1G-5 512MB : 64M x 64 PC3200A Unbuffered DDR DIMM 184pin Unbuffered DDR DIMM Based on DDR400A 32Mx8 SDRAM Features • 64Mx64 Unbuffered DDR DIMM based on 32Mx8 DDR SDRAM • DRAM DLL aligns DQ and DQS transitions with clock transitions • JEDEC Standard 184-pin Dual In-Line Memory Module
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NT512D64S8HB1G-5
512MB
PC3200A
184pin
DDR400A
32Mx8
64Mx64
184-pin
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PDF
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Untitled
Abstract: No abstract text available
Text: NT256D64S88B1G-5 256MB : 32M x 64 PC3200A Unbuffered DDR DIMM 184pin Unbuffered DDR DIMM Based on DDR400A 32Mx8 SDRAM Features • 32Mx64 Unbuffered DDR DIMM based on 32Mx8 DDR SDRAM • DRAM DLL aligns DQ and DQS transitions with clock transitions • JEDEC Standard 184-pin Dual In-Line Memory Module
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NT256D64S88B1G-5
256MB
PC3200A
184pin
DDR400A
32Mx8
32Mx64
184-pin
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PDF
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NT256D64S88B1G-5T
Abstract: DDR400 DDR400A NT256D64S88B1G NT256D64S88B1G-5 PC3200
Text: NT256D64S88B1G 256MB : 32M x 64 PC3200 Unbuffered DDR DIMM 184pin Unbuffered DDR DIMM Based on DDR400 32Mx8 SDRAM Features • 32Mx64 Unbuffered DDR DIMM based on 32Mx8 DDR SDRAM • DRAM DLL aligns DQ and DQS transitions with clock transitions • JEDEC Standard 184-pin Dual In-Line Memory Module
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NT256D64S88B1G
256MB
PC3200
184pin
DDR400
32Mx8
32Mx64
184-pin
PC3200A
NT256D64S88B1G-5T
DDR400A
NT256D64S88B1G
NT256D64S88B1G-5
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PDF
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48TT
Abstract: PC2100 PC2700 PC3200 ASM4SSTVF16857 ASM4SSTVF16857-48TT ASM5CVF857 JC42
Text: ASM4SSTVF16857 November 2003 rev v1.0 DDR 14-Bit Registered Buffer Features • To ensure that outputs are at a defined logic state before a Fully JEDEC JC40 - JC42.5 compliant for DDR1 applica- stable clock has been supplied, RESETB must be held at a tions to include: PC1600, PC2100, PC2700 & PC3200.
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ASM4SSTVF16857
14-Bit
PC1600,
PC2100,
PC2700
PC3200.
48TT
PC2100
PC2700
PC3200
ASM4SSTVF16857
ASM4SSTVF16857-48TT
ASM5CVF857
JC42
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PDF
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DDR DIMM pinout micron 184
Abstract: MT9VDDT1672A MT9VDDT1672AG-40B MT9VDDT3272A MT9VDDT3272AG-40B PC3200
Text: 128MB, 256MB x72, ECC , PC3200 184-Pin DDR SDRAM DIMM DDR SDRAM DIMM MT9VDDT1672A – 128MB MT9VDDT3272A – 256MB For the latest data sheet, please refer to the Micronâ Web site: www.micron.com/moduleds Features Figure 1: 184-Pin DIMM (MO-206) • JEDEC-standard 184-pin dual in-line memory
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128MB,
256MB
PC3200
184-Pin
MT9VDDT1672A
128MB
MT9VDDT3272A
MO-206)
DDR DIMM pinout micron 184
MT9VDDT1672A
MT9VDDT1672AG-40B
MT9VDDT3272A
MT9VDDT3272AG-40B
PC3200
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PDF
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NT512D64S8HB1G-5T
Abstract: 512mb 2.5v ddr pc3200 cl3 32mx8 DDR400 DDR400B NT512D64S8HB1G NT512D64S8HB1G-5 PC3200
Text: NT512D64S8HB1G-5 512MB : 64M x 64 PC3200 Unbuffered DDR DIMM 184pin Unbuffered DDR DIMM Based on DDR400 32Mx8 SDRAM Features • 64Mx64 Unbuffered DDR DIMM based on 32Mx8 DDR SDRAM • DRAM DLL aligns DQ and DQS transitions with clock transitions • JEDEC Standard 184-pin Dual In-Line Memory Module
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NT512D64S8HB1G-5
512MB
PC3200
184pin
DDR400
32Mx8
64Mx64
184-pin
PC3200A
NT512D64S8HB1G-5T
512mb 2.5v ddr pc3200 cl3 32mx8
DDR400B
NT512D64S8HB1G
NT512D64S8HB1G-5
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PDF
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09 0134 70 02
Abstract: No abstract text available
Text: NT256D64S88B1G-5 256MB : 32M x 64 PC3200A Unbuffered DDR DIMM 184pin Unbuffered DDR DIMM Based on DDR400A 32Mx8 SDRAM Features • 32Mx64 Unbuffered DDR DIMM based on 32Mx8 DDR SDRAM • DRAM DLL aligns DQ and DQS transitions with clock transitions • JEDEC Standard 184-pin Dual In-Line Memory Module
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NT256D64S88B1G-5
256MB
PC3200A
184pin
DDR400A
32Mx8
32Mx64
184-pin
09 0134 70 02
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PDF
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NT512D64S8HB1G-5T
Abstract: DIMM DDR400 PC3200 Nanya Technology SSTL-2 DDR400 DDR400B NT512D64S8HB1G NT512D64S8HB1G-5 PC3200
Text: NT512D64S8HB1G 512MB : 64M x 64 PC3200 Unbuffered DDR DIMM 184-pin Unbuffered DDR DIMM Based on DDR400 32Mx8 SDRAM Features • 64Mx64 Unbuffered DDR DIMM based on 32Mx8 DDR SDRAM • DRAM DLL aligns DQ and DQS transitions with clock transitions • JEDEC Standard 184-pin Dual In-Line Memory Module
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NT512D64S8HB1G
512MB
PC3200
184-pin
DDR400
32Mx8
64Mx64
PC3200A
NT512D64S8HB1G-5T
DIMM DDR400 PC3200
Nanya Technology
SSTL-2
DDR400B
NT512D64S8HB1G
NT512D64S8HB1G-5
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PDF
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Untitled
Abstract: No abstract text available
Text: NT256D64S88B1G-5 256MB : 32M x 64 PC3200A Unbuffered DDR DIMM 184pin Unbuffered DDR DIMM Based on DDR400A 32Mx8 SDRAM Features • 32Mx64 Unbuffered DDR DIMM based on 32Mx8 DDR SDRAM • DRAM DLL aligns DQ and DQS transitions with clock transitions • JEDEC Standard 184-pin Dual In-Line Memory Module
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NT256D64S88B1G-5
256MB
PC3200A
184pin
DDR400A
32Mx8
32Mx64
184-pin
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PDF
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Untitled
Abstract: No abstract text available
Text: NT512D64S8HB1G-5 512MB : 64M x 64 PC3200A Unbuffered DDR DIMM 184pin Unbuffered DDR DIMM Based on DDR400A 32Mx8 SDRAM Features • 64Mx64 Unbuffered DDR DIMM based on 32Mx8 DDR SDRAM • DRAM DLL aligns DQ and DQS transitions with clock transitions • JEDEC Standard 184-pin Dual In-Line Memory Module
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NT512D64S8HB1G-5
512MB
PC3200A
184pin
DDR400A
32Mx8
64Mx64
184-pin
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PDF
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Untitled
Abstract: No abstract text available
Text: 64MB, 128MB x64 PC3200 184-PIN DDR SDRAM DIMM DDR SDRAM DIMM MT4VDDT864A – 64MB (ADVANCE)‡ MT4VDDT1664A – 128MB For the latest data sheet, please refer to the Micronâ Web site: www.micron.com/moduleds Features Figure 1: 184-Pin DIMM (MO-206) • JEDEC standard 184-pin, dual in-line memory
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128MB
PC3200
184-PIN
184-pin,
400MT/s
PC3200
MT4VDDT1664A
09005aef80b56c1e
16x64AG
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PDF
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Untitled
Abstract: No abstract text available
Text: 64MB, 128MB x64 PC3200 184-PIN DDR SDRAM DIMM DDR SDRAM DIMM MT4VDDT864A – 64MB (ADVANCE)‡ MT4VDDT1664A – 128MB For the latest data sheet, please refer to the Micronâ Web site: www.micron.com/moduleds Features Figure 1: 184-Pin DIMM (MO-206) • JEDEC standard 184-pin, dual in-line memory
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Original
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128MB
PC3200
184-PIN
184-pin,
400MT/s
PC3200
MT4VDDT1664A
09005aef80b56c1e
16x64AG
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PDF
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XAPP851
Abstract: ddr phy VIRTEX-5 DDR PHY ddr phy design DDR400 JESD79E PC3200 sdram pcb layout ddr IDELAY x851
Text: Application Note: Virtex-5 Family DDR SDRAM Controller Using Virtex-5 FPGA Devices R Author: Toshihiko Moriyama and Rich Chiu XAPP851 v1.1 July 14, 2006 Summary This application note describes a 200-MHz DDR SDRAM (JEDEC DDR400, PC3200 standard) controller implemented in a Virtex -5 device. This implementation uses IDELAY elements to
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XAPP851
200-MHz
DDR400,
PC3200
DDR400
pnotes/xapp851
16-bit
200-MHz
PC3200)
XAPP851
ddr phy
VIRTEX-5 DDR PHY
ddr phy design
DDR400
JESD79E
sdram pcb layout ddr
IDELAY
x851
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PDF
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PC3200 ecc
Abstract: PC3200
Text: 64MB, 128MB x72 PC3200 184-PIN DDR SDRAM DIMM DDR SDRAM DIMM MT5VDDT872A – 64MB (ADVANCE)‡ MT5VDDT1672A – 128MB For the latest data sheet, please refer to the Micronâ Web site: www.micron.com/moduleds Features Figure 1: 184-Pin DIMM (MO-206) • JEDEC standard 184-pin, dual in-line memory
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128MB
PC3200
184-PIN
MT5VDDT872A
MT5VDDT1672A
MO-206)
184-pin,
400MT/s
PC3200 ecc
PC3200
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PDF
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NT256D72S89B0G-5T
Abstract: DDR400 DDR400B PC3200 dimm ddr pc3200
Text: NT256D72S89B0G 256MB : 32M x 72 PC3200 Unbuffered DDR DIMM 184pin Unbuffered DDR DIMM with ECC Based on DDR400 32Mx8 SDRAM Features • 32Mx72 Unbuffered DDR DIMM based on 32Mx8 DDR SDRAM • DRAM DLL aligns DQ and DQS transitions with clock transitions • JEDEC Standard 184-pin Dual In-Line Memory Module
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NT256D72S89B0G
256MB
PC3200
184pin
DDR400
32Mx8
32Mx72
184-pin
PC3200B
NT256D72S89B0G-5T
DDR400B
dimm ddr pc3200
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PDF
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MT46V32M16P
Abstract: No abstract text available
Text: 128MB, 256MB x72, SR PC3200 184-PIN DDR SDRAM UDIMM DDR SDRAM DIMM MT5VDDT1672A – 128MB MT5VDDT3272A – 256MB For the latest data sheet, please refer to the Micron Web site: www.micron.com/products/modules Features Figure 1: 184-Pin DIMM (MO-206) • JEDEC standard 184-pin, dual in-line memory
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Original
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128MB,
256MB
PC3200
184-PIN
184-pin,
400MT/s
PC3200
128MB
09005aef80cb210c,
MT46V32M16P
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PDF
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Untitled
Abstract: No abstract text available
Text: 64MB, 128MB x72 PC3200 184-PIN DDR SDRAM DIMM DDR SDRAM DIMM MT5VDDT872A – 64MB (ADVANCE)‡ MT5VDDT1672A – 128MB For the latest data sheet, please refer to the Micronâ Web site: www.micron.com/moduleds Features Figure 1: 184-Pin DIMM (MO-206) • JEDEC standard 184-pin, dual in-line memory
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Original
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128MB
PC3200
184-PIN
MT5VDDT872A
MT5VDDT1672A
MO-206)
184-pin,
400MT/s
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PDF
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