Please enter a valid full or partial manufacturer part number with a minimum of 3 letters or numbers

    LOGIC DIAGRAM OF IC 74LS10 Search Results

    LOGIC DIAGRAM OF IC 74LS10 Result Highlights (5)

    Part ECAD Model Manufacturer Description Download Buy
    74HC4053FT Toshiba Electronic Devices & Storage Corporation CMOS Logic IC, SPDT(1:2)/Analog Multiplexer, TSSOP16B, -40 to 125 degC Visit Toshiba Electronic Devices & Storage Corporation
    74HC4051FT Toshiba Electronic Devices & Storage Corporation CMOS Logic IC, SP8T(1:8)/Analog Multiplexer, TSSOP16B, -40 to 125 degC Visit Toshiba Electronic Devices & Storage Corporation
    DCL541A01 Toshiba Electronic Devices & Storage Corporation Digital Isolator / VDD=2.25~5.5V / 150Mbps / 4 channel(F:R=3:1) / Default Output Logic: Low / Input disable Visit Toshiba Electronic Devices & Storage Corporation
    DCL542H01 Toshiba Electronic Devices & Storage Corporation Digital Isolator / VDD=2.25~5.5V / 150Mbps / 4 channel(F:R=2:2) / Default Output Logic: High / Output enable Visit Toshiba Electronic Devices & Storage Corporation
    DCL541B01 Toshiba Electronic Devices & Storage Corporation Digital Isolator / VDD=2.25~5.5V / 150Mbps / 4 channel(F:R=3:1) / Default Output Logic: High / Input disable Visit Toshiba Electronic Devices & Storage Corporation

    LOGIC DIAGRAM OF IC 74LS10 Datasheets Context Search

    Catalog Datasheet MFG & Type PDF Document Tags

    HLMP-3000

    Abstract: optocoupler hcpl 4200 equivalent fabrication of an isolation circuit using optocoupler HCPL-4100 HCPL-4200 2N3740 HCPL4100 HCPL-4100 HCPL4200 HCPL-4200 RS-423
    Text: Designing with the HCPL-4100 and HCPL-4200 Current Loop Optocouplers Application Note 1018 Preface Avago Technologies produces a comprehensive line of optocouplers which address different speed and current gain requirements for isolation interface circuits. New


    Original     		PDF HCPL-4100 HCPL-4200 HCPL-4100 3266A 5953-9359E HLMP-3000 optocoupler hcpl 4200 equivalent fabrication of an isolation circuit using optocoupler HCPL-4100 HCPL-4200 2N3740 HCPL4100 HCPL4200 HCPL-4200 RS-423

    pin diagram of 74109

    Abstract: 74109 74109 dual JK PIN CONFIGURATION 74109 TTL 74109 1N3064 1N916 74LS 74LS109 74LS109A
    Text: 74109, LS109A Signetics Flip-Flops Dual J-K Positive Edge-Triggered Flip-Flop Product Specification Logic Products TYPICAL f MAX TYPICAL SUPPLY CURRENT TOTAL 74109 33MHz 9mA 74LS109A 33MHz 4mA DESCRIPTION The '109 is dual positive edge-triggered JK-type flip-flop featuring individual J, K,


    OCR Scan     		PDF LS109A 1N916, 1N3064, 500ns pin diagram of 74109 74109 74109 dual JK PIN CONFIGURATION 74109 TTL 74109 1N3064 1N916 74LS 74LS109 74LS109A

    RS flip flop IC

    Abstract: M74LS109AP T flip flop pin configuration Toggle flip flop IC JK flip flop IC 20-PIN toggle type flip flop ic
    Text: MITSUBISHI LSTTLs M 74LS109AP DUAL J-K POSITIVE EDGE-TRIGGERED FLIP FLO P WITH S E T AND R ESE T DESCRIPTION PIN C O NFIG URATIO N TOP V IEW The M74LS109AP is a semiconductor integrated circuit containing 2 J-K positive edge-triggered flip-flop circuits


    OCR Scan     		PDF M74LS109AP M74LS109AP 16-PIN 20-PIN RS flip flop IC T flip flop pin configuration Toggle flip flop IC JK flip flop IC toggle type flip flop ic

    74LS109AP

    Abstract: M74LS109 flip flop RS M74LS109AP
    Text: MITSUBISHI LSTTLs M 74LS109A P DUAL J-K P O S IT IV E EDGE-TRIGGERED F L IP FLOP W IT H SET AND RESET DESCRIPTION PIN CONFIGURATION TOP VIEW The M74LS109AP is a semiconductor integrated circu it containing 2 J-K positive edge-triggered flip -flo p circuits


    OCR Scan     		PDF 74LS109A M74LS109AP b2LHfl27 0013Sbl 14-PIN 16-PIN 20-PIN 74LS109AP M74LS109 flip flop RS

    74LS107n

    Abstract: 74107PC IC 74LS107
    Text: 107 CONNECTION DIAGRAM P IN O U T A oft 54/74107 O ' 54LS/74LS107^ n o r D UAL JK FLIP-FLO P With Separate Clears and Clocks Ji ^ DESCRIPTION— T he '107 dual J K master/slave flip-flops have a separate clo ck for each flip-flop. Inputs to the master section are controlled by the


    OCR Scan     		PDF 54LS/74LS107^ 54/74LS CLS107) 74LS107n 74107PC IC 74LS107

    Untitled

    Abstract: No abstract text available
    Text: GD54/74LS109A DUAL POSITIVE-EDGE- TRIGGERED J-K FLIP-FLOPS Feature Pin Configuration • Positive Edge-Triggering • Direct Set and reset inputs • J and K inputs • Q and Q outputs Vcc CLR2 J2 K2 C LK 2 PR2 Q2 QS R RRRFI R HR y Description This device contains two independent positiveedge-triggered J-K flip-flops with complementary out­


    OCR Scan     		PDF GD54/74LS109A

    M74LS10P

    Abstract: mitsubishi air conditioning 20-PIN 74LS10P
    Text: MITSUBISHI LSTTLs M 74LS10P T R IP L E 3 -IN P U T P O S IT IV E NAND GATES DESCRIPTION The M 74LS 10P is a semiconductor integrated circuit containing three triple-input positive N A N D and negative N O R gates. FEATURES • High breakdown input voltage V | ^ 15 V


    OCR Scan     		PDF M74LS10P b2LHfl27 0013Sbl 14-PIN 16-PIN 20-PIN M74LS10P mitsubishi air conditioning 74LS10P

    IC 74107

    Abstract: IC 74LS107 74LS107 LS107
    Text: Signelics 74107, LS107 Flip-Flops Dual J-K Flip-Flop Product Specification Logic Products DESCRIPTION transferred to the slave on the H IG H -toLO W Clock transition. For these devices TYPICAL f MAX TYPICAL SUPPLY CURRENT TOTAL 74107 20MHz 20mA 74LS107 45MHz


    OCR Scan     		PDF LS107 1N916, 1N3064, 500ns 500ns IC 74107 IC 74LS107 74LS107 LS107

    74LS10P

    Abstract: M74LS10P
    Text: M IT S U B IS H I L S T T L s M 74LS10P TRIPLE 3-IN P U T POSITIVE NAND GATES DESCRIPTION The M 74LS 10P is a semiconductor integrated circuit containing three triple-input positive N A N D and negative N O R gates. FEATURES • High breakdown input voltage V | ^ 15 V


    OCR Scan     		PDF 74LS10P 500ns, b2LHfl27 0013Sbl 14-PIN 16-PIN 20-PIN 74LS10P M74LS10P

    74LS115

    Abstract: 74LS273 74LS189 equivalent 74LS00 QUAD 2-INPUT NAND GATE 74LS265 fan-in and fan out of 7486 74LS93A 74LS181 74LS247 replacement MR 31 relay
    Text: F A IR C H IL D LOW POWER S C H O T T K Y D A TA BOOK ERRATA SHEET 1977 Device Page Item Schematic 2-5 Figure 2-6. Blocking diode in upper right is reversed. Also, diode con­ necting first darlington emitter to output should have series resistor. LS33 5-25


    OCR Scan     		PDF

    dm8130

    Abstract: 54175 DM74367 KS 2102 7486 ic truth table signetics 2502 ci 8602 gn block diagram ci 8602 gn 74s281 DM74LS76
    Text: 19 7 6 N atio n al S e m ico n d u cto r C o rp . p 1 ? I m • ' % TTL Data Book D EV IC E MIL i 2502 2503 2504 5400 54H00 54L00 54LS00 5401 54H01 54L01 54LS01 5402 54L02 54LS02 5403 54L03 54LS03 5404 54H04 54L04 54LS04 5405 54H05 54L05 54LS05 5406 5407 5408


    OCR Scan     		PDF 54H00 54L00 54LS00 54H01 54L01 54LS01 54L02 54LS02 54L03 54LS03 dm8130 54175 DM74367 KS 2102 7486 ic truth table signetics 2502 ci 8602 gn block diagram ci 8602 gn 74s281 DM74LS76

    sn 74373

    Abstract: SN 74114 logic diagram of ic 74112 IC 7486 xor IC 7402, 7404, 7408, 7432, 7400 7486 xor IC sn 74377 IC TTL 7486 xor IC TTL 7495 diagram and truth table IC 74374
    Text: PLS-WS/SN MAX+PLUS II Programmable Logic Software for Sun Workstations Data Sheet September 1991, ver. 1 Features J J □ □ □ J □ IJ Softw are supp ort for Classic, M A X 5000, M A X 7000, and S T G EPLD s Runs on Sun S P A R C s ta tio n s with S u n O S version 4.1.1 or h igher


    OCR Scan     		PDF

    triac tag 8518

    Abstract: 70146 DS3654 X2864AD 7 segment display RL S5220 TC9160 la 4440 amplifier circuit diagram 300 watt philips ecg master replacement guide vtl 3829 A-C4 TCA965 equivalent
    Text: 1985 0 / 0 / CONTENTS VOLUME I Introduction to IC MASTER 3 Advertisers’ Index 8 Master Selection Guide Function Index I0 Part Number Index 40 Part Number Guide 300 Logo Guide 346 Application Note Directory 349 Military Parts Directory 50I Testing 506 Cross Reference


    OCR Scan     		PDF

    DM74367

    Abstract: 54175 71ls97 DM74109 DM8160 om541 ci 8602 gn block diagram 5401 DM transistor 74L10 74S136
    Text: N ational Semiconductor Section 1 - 54/74 SSI DEVICES Connection Diagram s • Electrical Tables Section 2 - 54/74 M SI DEVICES Section 3 - National Semiconductor PROPRIETARY DEVICES Section 4 - National Semiconductor ADDITIONAL D EV KES t o NATIONAL Manufactured under one or more of the fo llowing U.S. patents: 3083262, 3189758, 3231797 , 3303356, 3317671, 3323071, 3381071, 3408542, 3421025, 3426423, 3440498, 3518750, 3519897, 3557431, 3560765,


    OCR Scan     		PDF

    Untitled

    Abstract: No abstract text available
    Text: TOSHIBA TC74HC109AP/AF/AFN Dual J-R Flip-Flop with Preset and Clear The TC74HC109A is a high speed CMOS DUAL J-FTFUPFLOP fabricated with silicon gate C2MOS technology. It achieves the high speed operation similar to equivalent LSTTL while maintaining the CMOS low power dissipation.


    OCR Scan     		PDF TC74HC109AP/AF/AFN TC74HC109A 63MHz TC74HC/HCT

    54LS109

    Abstract: 54LS109DMQB 54LS109FMQB DM54LS109AJ DM54LS109AW DM74LS109A DM74LS109AN J16A M16A
    Text: E M IC D N D U C T O R t General Description This device contains tw o independent positive-edge-triggered J-K flip-flops w ith com plem entary outputs. The J and K data is accepted by the flip-flop on the rising edge of the clock pulse. T he triggering occurs at a vo lt­


    OCR Scan     		PDF DM74LS109A 16-Lead DM74LS109AN 54LS109FMQB DM54LS109AW 54LS109 54LS109DMQB DM54LS109AJ DM74LS109A J16A M16A

    Untitled

    Abstract: No abstract text available
    Text: TC74HC107AP/AF/AFN D U A L J - K FL IP FLOP WITH CL EAR The TC74HC107A is a h ig h speed CMOS D U A L J - K F L IP -F L O P fa b ric a te d w ith silicon g ate C 2 MOS technology. It achieves the high speed o p eratio n s im ila r to eq u iv alen t L ST T L while m a in ta in in g the CMOS low pow er


    OCR Scan     		PDF TC74HC107AP/AF/AFN TC74HC107A TC74HC107AP/AF/AFN-3 TC74HC107AP/AF/AFN-4

    IC AND GATE 7408 specification sheet

    Abstract: 74LS183 74LS96 SN 74168 7486 XOR GATE IC 74LS192 IC 7402, 7404, 7408, 7432, 7400 IC 7486 for XOR gate IC 74183 74LS193 function table
    Text: PLS-EDIF Bidirectional EDIF Netlist Interface to MAX+PLUS Software Data Sheet September 1991, ver. 3 Features u J Provides a bidirectional netlist interface b etw ee n M A X + P L U S and other m ajor C A E softw are packages Sup ports the industry-standard Electronic Design Interchange Format


    OCR Scan     		PDF

    isa bus interfacing with microprocessor 8088

    Abstract: 8085 timing diagram for interrupt 8080a intel microprocessor pin diagram 8085 schematic with hardware reset 80586 u1j marking code quart intel 8080A instruction set i8231 8085 intel microprocessor block diagram
    Text: XR82C684 j C CMOS Quad Channel UART QUART 'E X A R September 1999-2 FEATURES • Four Full-Duplex, Independent Channels • Two Multi-function 16-bit Counter/Timers • Asynchronous Receiver and Transmitter • • Quadruple-Buffered Receivers and Transmitters


    OCR Scan     		PDF XR82C684 16-bit 34E2blfi XR82C684 34E2blà D01413S isa bus interfacing with microprocessor 8088 8085 timing diagram for interrupt 8080a intel microprocessor pin diagram 8085 schematic with hardware reset 80586 u1j marking code quart intel 8080A instruction set i8231 8085 intel microprocessor block diagram

    74107 pin diagram

    Abstract: 74107 74LS107 74107 flip flop H/CI 74107 pin configuration 74LS107 1N3064 1N916 74LS LS107
    Text: 74107, LS107 Signetics Flip-Flops Dual J-K Flip-Flop Product Specification Logic Products DESCRIPTION Th e '1 0 7 is a dual flip-flop with individual J, K, Clock and direct R eset inputs. The 7 4 1 0 7 Is a positive pulse-triggered flip­ flop. JK information is loaded into the


    OCR Scan     		PDF 74LS107 1N916, 1N3064, 500ns 74107 pin diagram 74107 74107 flip flop H/CI 74107 pin configuration 74LS107 1N3064 1N916 74LS LS107

    J-K Flip flops

    Abstract: No abstract text available
    Text: MITSUBISHI HIGH S P E E D CMOS M74HC107P/FP/DP DUAL J-K F L I P - F L O P WITH R E S E T DESCRIPTION The M74HC107 is a semiconductor integrated circuit con­ sisting of two negative-edge triggered J-K flip flops with in­ dependent control inputs PIN CONFIGURATION TOP VIEW


    OCR Scan     		PDF M74HC107P/FP/DP M74HC107 50MHz 10/uW/package, 74LSTTL 14P2P 14-PIN 16P2P 16-PIN 20P2V J-K Flip flops

    54LS10DMQB

    Abstract: DM74LS10N 54LS10 54LS10FMQB 54LS10LMQB DM54LS10J DM54LS10W DM74LS10 DM74LS10M E20A
    Text: S E M IC O N D U C T O R tm DM74LS10 Triple 3-Input NAND Gates General Description This device contains three independent gates each of which perform s the logic N AND function. Features • A lternate M ilitary/Aerospace device 54LS10 is available. C ontact a Fairchild Sem iconductor Sales


    OCR Scan     		PDF DM74LS10 54LS10) 54LS10DMQB, 54LS10FMQB, 54LS10LMQB, DM54LS10J, DM54LS10W, DM74LS10M DM74LS10N 54LS10DMQB 54LS10 54LS10FMQB 54LS10LMQB DM54LS10J DM54LS10W DM74LS10 E20A

    74LS109AN

    Abstract: 12111 74ls109am
    Text: I R C H I I - D EM I C O N D U C T O R T General Description This device contains tw o independent positive-edge-triggered J-K flip-flops w ith com plem entary outputs. The J and K data is accepted by the flip-flop on the rising edge of the clock pulse. The triggering occurs at a v o lt­


    OCR Scan     		PDF DM74LS109A DM74LS109A 74LS109AN 12111 74ls109am

    TT 2141

    Abstract: 74LS10 74LS TTL LC74HC10M cmos 74ls10 74LS series nand gates
    Text: l à e d~| ? cn 7 D 7 b G o p a b a a '3 SANYO SEMICONDUCTOR CORP • ' T - M 5 - 2 .1 LC74HC10M C M O S High-Speed Standard Logic L C 7 4 H C Series 3034 A i .¡S' ■ *• , Triple 3-Input N AND Gate -» Ï Z 14 1 A . Features ' " • The L C 7 4 H C 1 0 M consists o f 3 identical 3-input N A N D gates.


    OCR Scan     		PDF LC74HC LC74HC10M 74LS10) 54LS/74LS Vss-65 10sec LC74HC10M) 034A-M14IC LC74HG10. TT 2141 74LS10 74LS TTL cmos 74ls10 74LS series nand gates