LRAL Search Results

earom

Abstract: ER2051 ER2051HR ER2051IR
Contextual Info: ER2051 ER2051IR ER2051 HR GEN LRAL INSI R UMf 'NT 512 Bit Electrically Alterable Read Only Memory • ■ ■ ■ ■ ■ 32 w o rd x 16 b it o rg a n iz a tio n 5 b it b in a ry a d d re s s in g + 5 , —28 V p o w e r s u p p lie s W o rd A lte ra b le

AY 3 8600

Contextual Info: GtN LRAL. INSI R U M fM AY-3-8607 Shooting Gallery FEATURES • Outputs include CCIR AY-3-8607 com patible com posite sync, co lo r burst location and blanking ■ O peration fro m a 3.579545MHz clock ■ One o r tw o player game ■ D ig ita l on-screen scoring

A9RV

Abstract: 5s a315 A327
Contextual Info: TOSHIBA TC514900AJLL-70/80 524,288 WORD X 9 BIT DYNAMIC RAM DESCRIPTION The TC514900AJLL is the new generation dynamic RAM organized 524,288 word by 9 bit. The TC514900AJLL utilizes Toshiba’s CMOS silicon gate process technology as well as advanced circuit

TC514170BJ-80

Abstract: tc514170 TC514170BJ80
Contextual Info: TOSHIBA TC514170BJ-70/80 262,144 WORD X 16 BIT DYNAMIC RAM DESCRIPTION The TC514170BJ is the new generation dynam ic RAM organized 262,144 word by 16 bit. The TC514170BJ utilizes T oshiba’s CM OS silicon gate process technology as well as advanced circuit techniques

TC528257

Abstract: n724
Contextual Info: TOSHIBA SILICON GATE CMOS TC528257 t a r g e t s p e c 262,144WORDS X 8BITS MULTIPORT DRAM DESCRIPTION The TC528257 is a 2M bit CM OS multiport m em ory equipped with a 262,144-w ords by 8 -bits dynam ic random access m em ory RAM port and a 512-words by 8 -bits static serial access m emory (SA M ) port. The

tc5118180

Abstract: TC5118180AJ TC5118180A A495 A509 TC511818 TC5118 TOSHIBA TSOP50-P-400 toshiba A500 A498
Contextual Info: TOSHIBA TC511818 QAJ/AFT-70/80 1,048,576 WORD X 18 BIT DYNAMIC RAM DESCRIPTION The TC5118180AJ/FT is the new generation dynamic RAM organized 1,048,576 word by 18 bit. The TC5118180AJ/AFT utilizes Toshiba’s CMOS silicon gate process technology as w ell as advanced circuit

SF229

Abstract: toshiba s105
Contextual Info: TOSHIBA TC528257 t a r g e t s il ic o n g a t e c m o s s p e c 262,144WORDS X 8BITS MULTIPORT DRAM DESCRIPTION T h e T C 5 2 8 2 5 7 is a 2M b it C M O S m u ltip o rt m e m o ry eq u ip p e d w ith a 2 6 2 ,1 4 4 -w o rd s b y ra n d o m a ccess m e m o ry R A M p o rt a n d a 5 1 2 -w o rd s by

Contextual Info: TOSHIBA TC51V16400BST-60/70 PRELIMINARY 4,194,304 WORD X 4 BIT DYNAMIC RAM Description TheTC 51V16400B ST is the new generation dynamic RAM organized 4,194,304 word by 4 bits. T heTC 51V16400B ST uti­ lizes Toshiba's CM O S silicon gate process technology as well as advanced circuit techniques to provide wide operating mar­

tc5117400f

Abstract: TC5117400J
Contextual Info: TOSHIBA TC5117400J/Z/FT-60/70 4,194,304 WORD X 4 BIT DYNAMIC RAM DESCRIPTION The TC5117400J/Z/FT-60/70 is the new generation dynamic RAM organized 4,194,304 word by 4 bit. The TC5117400J/Z/FT-60/70 utilizes Toshiba’s CMOS silicon gate process technology as well as advanced

TC514100

Abstract: 514100A
Contextual Info: 4,194,304 WORD X 1 BIT DYNAMIC RAM DESCRIPTION THE TC514100A is the new generation dynamic RAM organized 4,194,304 word by 1 bit. The TC514410ASJ/AZ/AFT utilizes Toshiba’s CMOS silicon gate process technology as well as advanced circuit

Contextual Info: Advance information Features • O rganization: 4 ,1 9 4 ,3 0 4 w o rd s x 4 bits • H ig h speed - 50/6 0 ns RAS access time - 2 5/ 3 0 ns column address access time - 10/12 ns CAS access time • Low p o w er consum ption - Active: 908 mW max - Standby: S.S mW max, CMOS I/O

T4 3560 B

Abstract: alps encoder alps rotary Encoder alps encoder 12 alps Encoder switch 0/alps Encoder switch alps encoder 26 rotary encoder specifications alps Alps encoder b
Contextual Info: Customer: No. KK-2007-4798 alps europe distribution Date: Dec. 20,2007 Attention: Your ref. No.: Your Part No.: EC11J0924801 SPECIFICATIONS ALPS' ; MODEL: EC11J0924801_ Spec. No.: Sample No.: F 5 1 3 5 8 7 3 M RECEIPT STATUS RECEIVED By Date Signature

Contextual Info: » « H Y U N D A I e r ie s 1M x 4H_bŸjt 5C1M40 S4 0D R3 ABM Sw ,th 4C A S PRELIMINARY DESCRIPTION The HY514403B is the new generation and fast dynamic RAM organized 1,048,576 x 4-bit. The HY514403B has four CASs CAS0-3 which control corresponding data I/O port in conjunction with OE(eg. CSSO controls DQO,

Contextual Info: blE D • MM^baG3 G0E32fi0 1T4 ■ H I T 2 H M 5 1 4 1 9 0 , H M 5 1 4 1 9 0 L S e r i e s -262,144-word x 18-bit Dynamic Random Access Memory HITACHI/ LOGIC/ARRAYS/ NEM The Hitachi HM 514190 are CM OS dynamic RAM organized as 262,144-w ord x 18-bit. HM 514190

Contextual Info: @ LG Semicon. Co. LTD Description Features The GM M 784000CS is a 4M x 8 bits Dynamic RAM Module which is assembled 8 pieces of 4M bit DRAM GM71C4100CJ, 4Mxl in 20/26 pin small out-line J-form on a 30 p in s i n g l e i n - l i n e p a c k a g e . Th e

Contextual Info: ADVANCE MT4 L C1M16CX S 1 MEG X 16 DRAM IURN blllSHT I3004b21 4HT p ilC R O N MICRON TECHNOLOGY INC SSE » DRAM X 1 6 D R A M m 1 M E G 5.0V SELF REFRESH (MT4C1M16CX S) 3.0/3.3V, SELF REFRESH (MT4LC1M16CX S) FEATURES PIN ASSIGNMENT (Top View) • Self Refresh, ie "Sleep Mode"

Contextual Info: HB56D132BR-8/10/12 1,048,576-Word x 32-Bit High Density Dynamic RAM Module • DESCRIPTION PIN DESCRIPTION The HB56D132BR is a 1M x 32 dynamic RAM module, mounted 8 pieces of 4Mbit DRAM HM514400JP sealed in SOJ package. An outline of the HB56D132BR is 72-pin single in-line package. There­

Contextual Info: TOSHIBA TC51V4400ASJL/AFTL80 1,048,576 WORD X 4 BIT DYNAMIC RAM DESCRIPTION The TC51V 4400ASJL/AFTL is the new generation dynam ic RAM organized 1,048,576 w ord by 4 bit. The TC51V 4400A SJL/AFTL utilizes T oshiba's CM OS silicon gate process technology as w ell as advanced

Contextual Info: AW i « »02 O rd& r & M U T o c\'b f\ HM514270, HM514270L Series Preliminary 262,144-word x 16-blt Dynamic Random Access Memory ^ H I T A T he H itachi H M 514270/L are CMOS dynamic R A M o rg a n iz e d as 2 6 2 ,1 4 4 -w o rd x 16-bit. HM514270/L have realized higher density, higher

Contextual Info: JUL i F «:• SM5361000 L /5361000A(L)/5361000B(L) January 1993 Rev 2 SMART Modular Trchnoiotscs SM5361000(L)/5361000A(L)/5361000B(L) 4MByte (IM x 36) CMOS DRAM Modules General Description Features The SM 5361000 is a high performance, 4-megabyte dynam ic RAM module organized as 1M words by 36 bits,

Contextual Info: N E C ELECTRONICS INC Ifl 1> Ê b M 27 sas oditld? i N-CHANNEL SILICON P O WE R PACKAGE DIMENSIONS aciuater contro Is,and pulse circuits • Low RDS cn) L « 1 I I f I I I234Ï673910 Î Drain to Source Voitase VDSS 1C0V Gaie to Source Vo1tajs VGSS ±20V

SGTL500

Abstract: DAP 011 regulator audio graphic equalizer i2c graphic equalizer SGTL5000 32QFN history of old system speech control circuitry SGTL5000
Contextual Info: Freescale Semiconductor Advance Information Document Number: SGTL5000 Rev. 3.0, 7/2010 Low Power Stereo Codec with Headphone Amp SGTL5000 The SGTL5000 is a Low Power Stereo Codec with Headphone Amp from Freescale, and is designed to provide a complete audio solution

Contextual Info: H igh Perform ance 2M x8 CMOS DRAM II ; AS4C2M8E0 AS4T.C2M8E0 II 2M X 8 CMOS EDO DRAM Prelim inary inform ation Features • O r g a n iz a tio n : 2 ,0 9 7 ,1 5 2 w o r d s x 8 b its • R e a d - m o d ify -w r ite • H ig h s p e e d • T T L -c o m p a tib le , th r e e - s ta te 1 / O

AZ2100-1A-24DE

Abstract: AZ2100-1A-12de LRA series AZ2100-1A-12D AZ2100-1C-24DE AZ2101-1C-12DE Magnet Fluxgate FLC 100 AZ2100 E44211 motor life Expectancy
Contextual Info: AZ2100 MINIATURE POWER RELAY FEATURES • Versatility of both PC and “Trace-Saver” quick-connect terminals on contacts • 30 Amp switching capability for both N.O. and N.C. contacts • 1 Form A, B and C contacts available • DC coils to 120 VDC • Life expectancy to 10 million operations