Untitled
Abstract: No abstract text available
Text: CCLD-054X-20-622.080 LVDS Clock Oscillator 5x7mm SMD, 3.3V Model CCLD-054X is a 662.080MHz LVDS Clock Oscillator operating at 3.3Volts. Enable/Disable function used for system testing is offered as a standard feature. Operating Temperature is from -40°C to +85°C with
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CCLD-054X-20-622
CCLD-054X
080MHz
20ppm
27-Jan-10
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Untitled
Abstract: No abstract text available
Text: CCLD-054X-20-622.080 LVDS Clock Oscillator 5x7mm SMD, 3.3V Model CCLD-054X is a 622.080 MHz LVDS Clock Oscillator operating at 3.3Volts. Enable/Disable function used for system testing is offered as a standard feature. Operating Temperature is from -40°C to +85°C with
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CCLD-054X-20-622
CCLD-054X
20ppm
07-May-12
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"Audio Amplifier"
Abstract: No abstract text available
Text: EB-1550 ETX Backplane USB2.0 CF 20-pin Power In Serial Port USB2.0 Reset Button LVDS CRT RJ-45 Speaker R Single Board Computer PCI Slot Speaker L PS/2 KB/MS IDE Audio ETX Backplane Specifications *PCI Slot: Standard PCI slot x 1 *LVDS Panel: Supports 24-bit single channel/48-bit dual
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EB-1550
20-pin
RJ-45
24-bit
channel/48-bit
RJ-45
RS-232
RS-232/422/485
"Audio Amplifier"
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SiT8208
Abstract: SiT9121
Text: SiT9120 Standard Frequency Differential Oscillator The Smart Timing Choice The Smart Timing Choice Features Applications 31 standard frequencies from 25 MHz to 212.5 MHz LVPECL and LVDS output signaling types 0.6 ps RMS phase jitter random over 12 kHz to 20 MHz bandwidth
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SiT9120
SiT9121
SiT9122
SiT8208
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Untitled
Abstract: No abstract text available
Text: LVDS VCXO SMD-version 2,5 / 3,3V KXO-V63 model frequency range frequency stability incl. temperature stability input voltage and load stability, aging. at -20° ~ +70°C at -40° ~ +85°C 27,0 ~ 700,0 MHz ±25 ppm ~ ±100 ppm ±25 ppm ~ ±100 ppm standard -20° ~ +70°C
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KXO-V63
KXO-V63T)
400ps
850ps
12kHz
20MHz)
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KXO-V63
Abstract: No abstract text available
Text: LVDS VCXO SMD-version 2,5 / 3,3V KXO-V63 model frequency range frequency stability incl. temperature stability input voltage and load stability, aging. at -20° ~ +70°C at -40° ~ +85°C 27,0 ~ 700,0 MHz ±25 ppm ~ ±100 ppm ±25 ppm ~ ±100 ppm standard -20° ~ +70°C
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KXO-V63
KXO-V63T)
400ps
850ps
12kHz
20MHz)
KXO-V63
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Untitled
Abstract: No abstract text available
Text: Standard Products UT200SpWPHY01 SpaceWire Physical Layer Transceiver Advanced Datasheet April 20, 2006 INTRODUCTION FEATURES 2-bit Serializer/Deserializer SerDes functionality LVDS physical layer Data rates to 200 Mbits/sec Data/Strobe transmit skew <500pS
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UT200SpWPHY01
500pS
MIL-STD-883
28-pin
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Untitled
Abstract: No abstract text available
Text: LVDS VCXO SMD-version frequency range frequency stability incl. temperature stability input voltage and load stability, aging. at -20° ~ +70°C at -40° ~ +85°C 27,0 ~ 700,0 MHz ±25 ppm ~ ±100 ppm ±25 ppm ~ ±100 ppm standard -20° ~ +70°C available -40° ~ +85°C =KXO-V63T
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KXO-V63T)
400ps
850ps
12kHz
20MHz)
KXO-V63
2011/65/EU
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MAX9377
Abstract: MAX9377EUA MAX9378 MAX9378EUA
Text: 19-2846; Rev 0; 4/03 Anything-to-LVPECL/LVDS Translators with Pin-Selectable Divide-by-Four Features ♦ Guaranteed 2GHz Switching Frequency ♦ Accept LVDS/LVPECL/Anything Inputs ♦ Pin-Selectable Divide-by-Four Function ♦ 421ps typ Propagation Delays (MAX9377)
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421ps
MAX9377)
100mV
MAX9377EUA
MAX9378EUA*
MAX9377/MAX9378
MAX9377
MAX9377EUA
MAX9378
MAX9378EUA
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MAX9378
Abstract: MAX9377 MAX9377EUA MAX9378EUA
Text: 19-2846; Rev 1; 7/03 Anything-to-LVPECL/LVDS Translators with Pin-Selectable Divide-by-Four Features ♦ Guaranteed 2GHz Switching Frequency ♦ Accept LVDS/LVPECL/Anything Inputs ♦ Pin-Selectable Divide-by-Four Function ♦ 421ps typ Propagation Delays (MAX9377)
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421ps
MAX9377)
100mV
MAX9377EUA
MAX9378EUA
MAX9377/MAX9378
MAX9378
MAX9377
MAX9377EUA
MAX9378EUA
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Untitled
Abstract: No abstract text available
Text: 19-2846; Rev 1; 7/03 Anything-to-LVPECL/LVDS Translators with Pin-Selectable Divide-by-Four The MAX9377/MAX9378 accept any differential input signal within the supply rails and with minimum amplitude of 100mV. Inputs are fully compatible with the LVDS, LVPECL, HSTL, and CML differential signaling
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MAX9377/MAX9378
100mV.
MAX9377
MAX9378
EIA/TIA-644
MAX9377/MAX9378
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Untitled
Abstract: No abstract text available
Text: SN65LVDS048 LVDS QUAD DIFFERENTIAL LINE RECEIVER SLLS415A – JUNE 2000 – REVISED SEPTEMBER 2000 D D D D D D D D D D D D D D >400 Mbps 200 MHz Signaling Rates Flow-Through Pinout Simplifies PCB Layout 50 ps Channel-to-Channel Skew (Typ) 200 ps Differential Skew (Typ)
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SN65LVDS048
SLLS415A
TIA/EIA-644
DS90LV048A
SLLU016B
SN65LVDS048D
SN65LVDS048DR
SN65LVDS048PW
SN65LVDS048PWR
SN65LVDS048AD
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metal detector plans
Abstract: SI5334A Si5334C-Axxxxx-GM JESD78 Si5334 SSTL-18 Si5334B-Axxxxx-GM SI5334D
Text: Si5334 P I N - C ONTR OLLED A N Y - F REQUENCY, A NY - O UTPUT Q U A D C L O C K G ENERATOR Features Applications Si5334 Transparent Top View OEB Pin Assignments VDDO0 Ordering Information: See page 24. CLK0B CLK0A Independent output voltage per
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Si5334
24-QFN
metal detector plans
SI5334A
Si5334C-Axxxxx-GM
JESD78
Si5334
SSTL-18
Si5334B-Axxxxx-GM
SI5334D
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MAX9110
Abstract: MAX9110EKA-T MAX9110ESA MAX9111 MAX9112 MAX9113
Text: 19-1771; Rev 0; 9/00 Single/Dual LVDS Line Drivers with Ultra-Low Pulse Skew in SOT23 Features ♦ Low 250ps max Pulse Skew for High-Resolution Imaging and High-Speed Interconnect ♦ Space-Saving 8-Pin SOT23 and SO Packages ♦ Pin-Compatible Upgrades to DS90LV017/017A
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250ps
DS90LV017/017A
DS90LV027/027A
500Mbps
MAX9112)
EIA/TIA-644
OT23-8
MAX9110ESA
MAX9112EKA-T
OT23-w
MAX9110
MAX9110EKA-T
MAX9110ESA
MAX9111
MAX9112
MAX9113
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5962 38535
Abstract: No abstract text available
Text: Standard Products UT54LVDS218 Deserializer Data Sheet May 24, 2002 FEATURES INTRODUCTION q q q q q 15 to 50MHz shift clock support 50% duty cycle on receiver output clock Low power consumption Cold sparing all pins Power-down mode <200µW max The UT54LVDS218 Deserializer converts the three LVDS data
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UT54LVDS218
50MHz
50MHz,
48-lead
5962 38535
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54LVDS218
Abstract: UT54LVDS218 LVDS217 marking RAD
Text: Standard Products UT54LVDS218 Deserializer Data Sheet April, 2002 FEATURES INTRODUCTION q q q q q 15 to 75 MHz shift clock support 50% duty cycle on receiver output clock Low power consumption Cold sparing all pins Power-down mode <200µW max The UT54LVDS218 Deserializer converts the three LVDS data
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UT54LVDS218
48-lead
54LVDS218
LVDS217
marking RAD
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LVDS 26 pin connector cable
Abstract: lvds 26 pin lvds cable LVDS connector lvds connector 20 pin LVDS 50 pin LVDS connector 20 pin 50-pin lvds LVDS connector 26 pin lvds 20 pin lcd 20 pin lcd lvds
Text: PCM-3532 Daughter Board for Gene Series Features LINE_IN External Jack MIC_IN External Jack LINE_OUT External Jack CD_IN Connectors LVDS 26-pin External Connector Two USB External Connectors S-Video Connector RCA External Jack PCM-3524 LVDS Transmitter/Receiver Module
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PCM-3532
26-pin
PCM-3524
PCM-3524
65MHz
290mV
TIA/EIA-644
LVDS 26 pin connector cable
lvds 26 pin
lvds cable
LVDS connector lvds connector 20 pin
LVDS 50 pin
LVDS connector 20 pin
50-pin lvds
LVDS connector 26 pin
lvds 20 pin lcd
20 pin lcd lvds
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SY58011U
Abstract: SY58012U SY58013U SY58020U SY58021U SY58022U SY89311U SY89830U SY89831U SY89832U
Text: www.micrel.com Precision Edge DC-to-6GHz Clock Fanout Buffers Smallest Package 16-Pin: 3mm x 3mm MLF™ 8 pin: 2mm x 2mm MLF™ Timing Solutions that Simplify Designs Highest Precision in the Industry ◆ ◆ ◆ ◆ CML Output Swing vs. Frequency Guaranteed ultra-low jitter: <10psPK-PK total jitter
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16-Pin:
10psPK-PK
110ps
800mV)
400mV)
200ps
M-0091
SY58011U
SY58012U
SY58013U
SY58020U
SY58021U
SY58022U
SY89311U
SY89830U
SY89831U
SY89832U
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54LVDS218
Abstract: LVDS217
Text: Standard Products UT54LVDS218 Deserializer Advanced Data Sheet February, 2002 FEATURES INTRODUCTION q q q q q 15 to 75 MHz shift clock support 50% duty cycle on receiver output clock Low power consumption Cold sparing all pins Power-down mode <200µW max
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UT54LVDS218
48-lead
54LVDS218
LVDS217
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MAX9126
Abstract: No abstract text available
Text: 19-1908; Rev 0; 5/01 KIT ATION EVALU E L B A AVAIL Quad LVDS Line Receivers with Integrated Termination Features ♦ Integrated Termination Eliminates Four External Resistors MAX9126 ♦ Pin Compatible with DS90LV032A ♦ Guaranteed 500Mbps Data Rate ♦ 300ps Pulse Skew (max)
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MAX9126)
DS90LV032A
500Mbps
300ps
TIA/EIA-644
MAX9125/MAX9126
MAX9125/MAX9126
500Mbps
250MHz)
MAX9126
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circuit diagram of 16-1 multiplexer design logic
Abstract: 10GBASE-ER demultiplexer truth table GR-63-CORE STM-64 stm 64 laser diode 1550 nm
Text: Data Sheet March 2003 CB64ER-Type 10.3 Gb/s Cooled Lightwave 300-Pin Transponder with 16-Ch. 644 Mb/s Multiplexer/Demultiplexer • ■ ■ ■ ■ ■ Features ■ ■ ■ ■ ■ ■ Supports long-reach 10GBASE-ER optical Ethernet Serial LAN-ER at data rate of 10.3125 Gb/s, with
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CB64ER-Type
300-Pin
16-Ch.
10GBASE-ER
16-channel
GR-63-CORE*
DS03-015
DS02-349)
circuit diagram of 16-1 multiplexer design logic
demultiplexer truth table
GR-63-CORE
STM-64
stm 64 laser diode 1550 nm
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Pin TO PIN compatible maxim
Abstract: No abstract text available
Text: 19-1991; Rev 0; 4/01 KIT ATION EVALU E L B A AVAIL Quad LVDS Line Driver Features ♦ Pin Compatible with DS90LV031A ♦ Guaranteed 800Mbps Data Rate ♦ 250ps Maximum Pulse Skew ♦ Conforms to TIA/EIA-644 LVDS Standard ♦ Single +3.3V Supply ♦ 16-Pin TSSOP and SO Packages
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DS90LV031A
800Mbps
250ps
TIA/EIA-644
16-Pin
MAX9124
800Mbps
400MHz)
Pin TO PIN compatible maxim
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Untitled
Abstract: No abstract text available
Text: Standard Products UT54LVDS218 Deserializer Advanced Data Sheet October 4, 2001 FEATURES INTRODUCTION q q q q q 15 to 75 MHz shift clock support 50% duty cycle on receiver output clock Low power consumption Cold sparing all pins Power-down mode <200µW max
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UT54LVDS218
48-lead
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Untitled
Abstract: No abstract text available
Text: Standard Products UT54LVDS218 Deserializer Advanced Data Sheet October 24, 2001 FEATURES INTRODUCTION q q q q q 15 to 75 MHz shift clock support 50% duty cycle on receiver output clock Low power consumption Cold sparing all pins Power-down mode <200µW max
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UT54LVDS218
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