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    LVPECL MULTIDROP Search Results

    LVPECL MULTIDROP Result Highlights (5)

    Part ECAD Model Manufacturer Description Download Buy
    MPC9229ACR2 Renesas Electronics Corporation LVPECL Clock Synthesizer Visit Renesas Electronics Corporation
    8N3S270EC-1028CDI Renesas Electronics Corporation LVPECL Frequency-Programmable Crystal Oscillator Visit Renesas Electronics Corporation
    8N3S270EC-1080CDI8 Renesas Electronics Corporation LVPECL Frequency-Programmable Crystal Oscillator Visit Renesas Electronics Corporation
    8N3S270KC-0074CDI8 Renesas Electronics Corporation LVPECL Frequency-Programmable Crystal Oscillator Visit Renesas Electronics Corporation
    8N3S270KC-1154CDI8 Renesas Electronics Corporation LVPECL Frequency-Programmable Crystal Oscillator Visit Renesas Electronics Corporation

    LVPECL MULTIDROP Datasheets Context Search

    Catalog Datasheet MFG & Type PDF Document Tags

    IN50

    Abstract: MAX9180 MAX9181 MAX9181EXT-T SC70-6
    Text: 19-2415; Rev 0; 4/02 Low-Jitter, Low-Noise LVPECL-to-LVDS Level Translator in an SC70 Package The MAX9181 is an LVPECL-to-LVDS level translator that accepts a single LVPECL input and translates it to a single LVDS output. It is ideal for interfacing between


    Original     		PDF MAX9181 400Mbps MAX9181 IN50 MAX9180 MAX9181EXT-T SC70-6

    LVPECL multidrop

    Abstract: IN50 MAX9180 MAX9181 MAX9181EXT-T SC70-6
    Text: 19-2415; Rev 1; 2/04 Low-Jitter, Low-Noise LVPECL-to-LVDS Level Translator in an SC70 Package The MAX9181 is an LVPECL-to-LVDS level translator that accepts a single LVPECL input and translates it to a single LVDS output. It is ideal for interfacing between


    Original     		PDF MAX9181 400Mbps MAX9181 LVPECL multidrop IN50 MAX9180 MAX9181EXT-T SC70-6

    Untitled

    Abstract: No abstract text available
    Text: 19-2415; Rev 1; 2/04 Low-Jitter, Low-Noise LVPECL-to-LVDS Level Translator in an SC70 Package The MAX9181 is an LVPECL-to-LVDS level translator that accepts a single LVPECL input and translates it to a single LVDS output. It is ideal for interfacing between


    Original     		PDF MAX9181 MAX9181â 400Mbps MAX9181

    LVPECL multidrop

    Abstract: LVPECL load XAPP237 balanced line driver receiver
    Text: Application Note: Virtex-E Family Virtex-E LVPECL Receivers in Multi-Drop Applications R XAPP237 v1.1 February 24, 2000 Author: Brian Von Herzen and Jon Brunetti Summary This application note describes how to use differential LVPECL (low-voltage positive emittercoupled logic) signaling for high-performance multi-drop applications with Virtex-E FPGAs.


    Original     		PDF XAPP237 LVPECL multidrop LVPECL load XAPP237 balanced line driver receiver

    Untitled

    Abstract: No abstract text available
    Text: 3.3V 2.5Gbps ANY INPUT-to-LVPECL DIFFERENTIAL TRANSLATOR Micrel, Inc. Precision Edge ® SY89327L Precision Edge SY89327L FEATURES Input accepts virtually all logic standards: • Single-ended: SSTL, TTL, CMOS • Differential: LVDS, HSTL, CML Guaranteed AC performance over temp and voltage:


    Original     		PDF SY89327L 400ps 200ps SY89327L M9999-071707

    SY55857L

    Abstract: SY89325LMGTR SY89327L SY89327LMITR sstl lvttl Translator microleadframe
    Text: Precision Edge ® SY89327L Precision Edge 3.3V 2.5Gbps ANY INPUT-to-LVPECL DIFFERENTIAL TRANSLATOR Micrel, Inc. SY89327L FEATURES • Input accepts virtually all logic standards: • Single-ended: SSTL, TTL, CMOS • Differential: LVDS, HSTL, CML ■ Guaranteed AC performance over temp and voltage:


    Original     		PDF SY89327L 400ps 200ps 10psPP M9999-072005 SY55857L SY89325LMGTR SY89327L SY89327LMITR sstl lvttl Translator microleadframe

    SY55857L

    Abstract: SY89327L SY89327LMITR
    Text: Precision Edge 3.3V 2.5Gbps ANY INPUT-to-LVPECL DIFFERENTIAL TRANSLATOR Micrel SY89327L Precision Edge™ SY89327L FEATURES • Input accepts virtually all logic standards: • Single-ended: SSTL, TTL, CMOS • Differential: LVDS, HSTL, CML ■ Guaranteed AC performance over temp and voltage:


    Original     		PDF SY89327L 400ps 200ps 10psp-p M9999-042704 SY55857L SY89327L SY89327LMITR

    SY89327LMGTR

    Abstract: SY55857L SY89327L SY89327LMITR
    Text: Precision Edge ® SY89327L Precision Edge 3.3V 2.5Gbps ANY INPUT-to-LVPECL DIFFERENTIAL TRANSLATOR Micrel, Inc. SY89327L FEATURES • Input accepts virtually all logic standards: • Single-ended: SSTL, TTL, CMOS • Differential: LVDS, HSTL, CML ■ Guaranteed AC performance over temp and voltage:


    Original     		PDF SY89327L 400ps 200ps 10psPP M9999-071707 SY89327LMGTR SY55857L SY89327L SY89327LMITR

    100MHz high-frequency generator

    Abstract: MAX9155 MAX9156 MAX9156EXT-T SC70-6
    Text: 19-2216; Rev 0; 10/01 Low-Jitter, Low-Noise LVPECL-to-LVDS Level Translator in an SC70 Package Features ♦ Tiny SC70 Package ♦ Ultra-Low Jitter 23psp-p Added Deterministic Jitter 223-1 PRBS 0.6psRMS Added Random Jitter ♦ 0.5ns (min) Transition Time Minimizes Radiated


    Original     		PDF 23psp-p 200Mbps ANSI/EIA/TIA-644 MAX9156EXT-T SC70-6 MAX9156 100MHz high-frequency generator MAX9155 MAX9156 MAX9156EXT-T SC70-6

    Untitled

    Abstract: No abstract text available
    Text: DS08MB200 www.ti.com SNLS197C – MAY 2006 – REVISED SEPTEMBER 2012 DS08MB200 Dual 800 Mbps 2:1/1:2 LVDS Mux/Buffer Check for Samples: DS08MB200 FEATURES 1 • • 2 • • Up to 800 Mbps data rate per channel LVDS/BLVDS/CML/LVPECL compatible inputs, LVDS compatible outputs


    Original     		PDF DS08MB200 SNLS197C DS08MB200 48-pin

    Untitled

    Abstract: No abstract text available
    Text: 19-2216; Rev 0; 10/01 Low-Jitter, Low-Noise LVPECL-to-LVDS Level Translator in an SC70 Package The MAX9156 operates from a single +3.3V supply and consumes only 10mA supply current over a -40°C to +85°C temperature range. It is available in a tiny 6-pin


    Original     		PDF MAX9156 MAX9155 23psp-p 200Mbps ANSI/EIA/TIA-644 MAX9156

    Untitled

    Abstract: No abstract text available
    Text: 19-2003; Rev 0; 4/01 800Mbps LVDS/LVPECL-to-LVDS 2 x 2 Crosspoint Switch The MAX9152 can be programmed to connect any input to either or both outputs, allowing it to be used in the following configurations: 2 ✕ 2 crosspoint switch, 2:1 mux, 1:2 demux, 1:2 splitter, or dual repeater. This flexibility makes the MAX9152 ideal for protection switching


    Original     		PDF 800Mbps MAX9152 MAX9152

    DS90CP22

    Abstract: MAX9152 MAX9152ESE MAX9152EUE
    Text: 19-2003; Rev 0; 4/01 800Mbps LVDS/LVPECL-to-LVDS 2 x 2 Crosspoint Switch The MAX9152 can be programmed to connect any input to either or both outputs, allowing it to be used in the following configurations: 2 ✕ 2 crosspoint switch, 2:1 mux, 1:2 demux, 1:2 splitter, or dual repeater. This flexibility makes the MAX9152 ideal for protection switching


    Original     		PDF 800Mbps MAX9152 120psPK-PK MAX9152 DS90CP22 MAX9152ESE MAX9152EUE

    Untitled

    Abstract: No abstract text available
    Text: 19-2003; Rev 0; 4/01 800Mbps LVDS/LVPECL-to-LVDS 2 x 2 Crosspoint Switch The MAX9152 can be programmed to connect any input to either or both outputs, allowing it to be used in the following configurations: 2 ✕ 2 crosspoint switch, 2:1 mux, 1:2 demux, 1:2 splitter, or dual repeater. This flexibility makes the MAX9152 ideal for protection switching


    Original     		PDF 800Mbps MAX9152 120psPK-PK MAX9152

    INSSTE32882

    Abstract: maxim dallas 2501 insstua32866 INSSTU32864 INSSTU32866 ttl crystal oscillator using CIRCUIT DIAGRAM INCUA877 ps 2501 dallas GSM home automation block diagram INCU877
    Text: Clocks and Timing Guide www.ti.com/clocks 2Q 2009 2 Clocks and Timing Guide ➔ Clocks and Timing Selection Tree Clocks by Function Clock Distribution Non- PLL Fanout Buffers PLL Buffers RF Synthesizers Clock Generation General Purpose Generator/Synthesizer


    Original     		PDF

    LVPECL multidrop

    Abstract: LVDS 31 pin DS08MB200 DS08MB200TSQ DS08MB200TSQX AN1194 lvds switch
    Text: DS08MB200 Dual 800 Mbps 1:2/2:1 LVDS Mux/Buffer General Description Features The DS08MB200 is a dual-port 1 to 2 repeater/buffer and 2 to 1 multiplexer. High-speed data paths and flow-through pinout minimize internal device jitter and simplify board layout. The differential inputs and outputs interface to LVDS or


    Original     		PDF DS08MB200 DS08MB200 CSP-9-111S2) LVPECL multidrop LVDS 31 pin DS08MB200TSQ DS08MB200TSQX AN1194 lvds switch

    AN-1194

    Abstract: DS08MB200 DS08MB200TSQ DS08MB200TSQX
    Text: DS08MB200 Dual 800 Mbps 2:1/1:2 LVDS Mux/Buffer General Description Features The DS08MB200 is a dual-port 1 to 2 repeater/buffer and 2 to 1 multiplexer. High-speed data paths and flow-through pinout minimize internal device jitter and simplify board layout. The differential inputs and outputs interface to LVDS or


    Original     		PDF DS08MB200 DS08MB200 100istered AN-1194 DS08MB200TSQ DS08MB200TSQX

    lvds buffer

    Abstract: DS15MB200TSQ DS15MB200TSQX AN-1187 AN-1194 DS15MB200
    Text: DS15MB200 Dual 1.5 Gbps 2:1/1:2 LVDS Mux/Buffer with Pre-Emphasis General Description Features The DS15MB200 is a dual-port 2 to 1 multiplexer and 1 to 2 repeater/buffer. High-speed data paths and flow-through pinout minimize internal device jitter and simplify board layout,


    Original     		PDF DS15MB200 DS15MB200 CSP-9-111S2) CSP-9-111S2. lvds buffer DS15MB200TSQ DS15MB200TSQX AN-1187 AN-1194

    lvds buffer

    Abstract: DS15MB200 DS15MB200TSQ DS15MB200TSQX AN-1187 AN-1194
    Text: DS15MB200 Dual 1.5 Gbps 2:1/1:2 LVDS Mux/Buffer with Pre-Emphasis General Description Features The DS15MB200 is a dual-port 2 to 1 multiplexer and 1 to 2 repeater/buffer. High-speed data paths and flow-through pinout minimize internal device jitter and simplify board layout,


    Original     		PDF DS15MB200 DS15MB200 CSP-9-111S2) CSP-9-111S2. lvds buffer DS15MB200TSQ DS15MB200TSQX AN-1187 AN-1194

    Untitled

    Abstract: No abstract text available
    Text: DS15MB200 Dual 1.5 Gbps 1:2/2:1 LVDS Mux/Buffer with Pre-emphasis General Description Features The DS15MB200 is a dual-port 1 to 2 repeater/buffer and 2 to 1 multiplexer. High-speed data paths and flow-through pinout minimize internal device jitter and simplify board layout, while pre-emphasis overcomes ISI jitter effects from


    Original     		PDF DS15MB200

    Untitled

    Abstract: No abstract text available
    Text: SCAN15MB200 www.ti.com SNLS188D – NOVEMBER 2005 – REVISED MAY 2006 Dual 1.5 Gbps 2:1/1:2 LVDS Mux/Buffer with Pre-Emphasis and IEEE 1149.6 Check for Samples: SCAN15MB200 FEATURES 1 • • 2 • • 1.5 Gbps data rate per channel Configurable off/on pre-emphasis drives lossy


    Original     		PDF SCAN15MB200 SNLS188D 48-pin SCAN15MB200

    Untitled

    Abstract: No abstract text available
    Text: DS08MB200 www.ti.com SNLS197D – MAY 2006 – REVISED MARCH 2013 DS08MB200 Dual 800 Mbps 2:1/1:2 LVDS Mux/Buffer Check for Samples: DS08MB200 FEATURES DESCRIPTION • • The DS08MB200 is a dual-port 1 to 2 repeater/buffer and 2 to 1 multiplexer. High-speed data paths and


    Original     		PDF DS08MB200 SNLS197D DS08MB200

    Untitled

    Abstract: No abstract text available
    Text: SCAN15MB200 www.ti.com SNLS188D – NOVEMBER 2005 – REVISED MAY 2006 Dual 1.5 Gbps 2:1/1:2 LVDS Mux/Buffer with Pre-Emphasis and IEEE 1149.6 Check for Samples: SCAN15MB200 FEATURES 1 • • 2 • • 1.5 Gbps data rate per channel Configurable off/on pre-emphasis drives lossy


    Original     		PDF SCAN15MB200 SNLS188D 48-pin SCAN15MB200

    RHS0048A

    Abstract: WQFN-48
    Text: DS08MB200 www.ti.com SNLS197D – MAY 2006 – REVISED MARCH 2013 DS08MB200 Dual 800 Mbps 2:1/1:2 LVDS Mux/Buffer Check for Samples: DS08MB200 FEATURES DESCRIPTION • • The DS08MB200 is a dual-port 1 to 2 repeater/buffer and 2 to 1 multiplexer. High-speed data paths and


    Original     		PDF DS08MB200 SNLS197D DS08MB200 48-pin RHS0048A WQFN-48