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    82V2108PXG Renesas Electronics Corporation 3.3V T1/E1/J1 OCTAL FRAMER Visit Renesas Electronics Corporation

    LXT FRAMER Datasheets Context Search

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    lxt388

    Abstract: LXT386 LXT380 LXT380BE LXT381 LXT384 LXT framer LXT38X iXA 160 Remote Switching Center
    Text: product brief Intel LXT380/381 Octal E1 Transceivers Intel® Delivers Intel Internet Exchange Architecture ® www.intel.com/ design/network Intel® introduces a family of T1/E1 3.3V transceivers that are pin-to-pin and software compatible. This LXT product series includes


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    PDF LXT380/381 LXT380 LXT381 LXT384, LXT386, LXT388 048Mbps USA/0101/1K/ASI/DC lxt388 LXT386 LXT380BE LXT381 LXT384 LXT framer LXT38X iXA 160 Remote Switching Center

    X1HB

    Abstract: MTC13 LXT625 131-G W J 50
    Text: DATA SHEET JUNE 1999 Revision 2.0 LXT6251 21 E1 SDH Mapper LXT General Description Features The LXT6251 21E1 Mapper performs asynchronous mapping and demapping of 21 E1 PDH signals into SDH. The PDH side interfaces with E1 LIUs and framers via NRZ Clock & Data, while the SDH side uses a standard


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    PDF LXT6251 VC-12 VC-12s, PDS-6251-8/99-2 X1HB MTC13 LXT625 131-G W J 50

    LXT380

    Abstract: LXT381 LXT384 LXT386 LXT388
    Text: product brief Intel LXT380/381 Octal E1 Line Interface Unit Intel Delivers Intel Internet Exchange Architecture ® Intel introduces a family of T1/E1 3.3V transceivers that are pin-to-pin and software compatible. This LXT product series includes the Intel® LXT380 and LXT381 detailed in this


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    PDF LXT380/381 LXT380 LXT381 LXT384, LXT386, LXT388 048Mbps USA/0501/3K/ASI/DC LXT381 LXT384 LXT386 LXT388

    TXN13600

    Abstract: IXF30009 IXF30011 stm 16 muxponder IXF30010 ixf193 IXF30007 muxponder stm 4 muxponder FEC 10G
    Text: Product Brief Intel IXF30009/30010/30011 Optical Transport Processors Intel® optical components are modular building blocks that enable networking equipment manufacturers to create standards-based products with shorter time-to-market and reduced development costs. Developers can use these


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    PDF IXF30009/30010/30011 IXF30009/30010/30011 IXF30001, IXF30003, IXF30005, 0504/DLC/S2D/RE/PDF TXN13600 IXF30009 IXF30011 stm 16 muxponder IXF30010 ixf193 IXF30007 muxponder stm 4 muxponder FEC 10G

    magneticless ethernet

    Abstract: magnetic less ethernet wireless communication paper presentation network interface card 802.3 circuit diagram magneticless gigabit Twinax carrier intel 21143 ip dslam LXT776 Dual Port Copper Gigabit Ethernet Card MTBF
    Text: Carrier Class Ethernet White Paper September 2001 ,Order Number: 249949-001 Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel’s Terms and Conditions of Sale for such products, Intel assumes no liability


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    RRUS 32

    Abstract: RRUS 01 RRUS 12 BBU RRU obsai virtex ucf file 6 lte RF Transceiver y2970 VIRTEX-5 GTX ethernet xilinx vhdl
    Text: OBSAI v3.3 DS612 September 16, 2009 Product Specification Introduction LogiCORE IP Facts The LogiCORE IP OBSAI core implements an OBSAI RP3 interface supporting RP3-01 at 768 Mbps, 1.5 Gbps, and 3 Gpbs using GTP or GTX transceivers available for Virtex -6 and Virtex-5 FPGAs. The OBSAI core can be


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    PDF DS612 RP3-01 16/LTE RRUS 32 RRUS 01 RRUS 12 BBU RRU obsai virtex ucf file 6 lte RF Transceiver y2970 VIRTEX-5 GTX ethernet xilinx vhdl

    RRUS 01

    Abstract: free source code for cdma transceiver using vhdl vhdl code for demultiplexer 16 to 1 using 4 to 1 BBU RRU vhdl code for multiplexer 8 to 1 using 2 to 1 lte RF Transceiver DS612 obsai RRUS VIRTEX-5
    Text: OBSAI v2.1 DS612 June 27, 2008 Product Specification Introduction LogiCORE IP Facts The LogiCORE IP OBSAI core implements an OBSAI RP3 interface supporting RP3-01 at 768 Mbps, 1.5 Gbps, and 3 Gpbs using RocketIO™ GTP or GTX transceivers available for Virtex -5 FPGAs. The OBSAI core can be


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    PDF DS612 RP3-01 RRUS 01 free source code for cdma transceiver using vhdl vhdl code for demultiplexer 16 to 1 using 4 to 1 BBU RRU vhdl code for multiplexer 8 to 1 using 2 to 1 lte RF Transceiver obsai RRUS VIRTEX-5

    vhdl code for demultiplexer

    Abstract: RRUS 01 BBU RRU free source code for cdma transceiver using vhdl obsai vhdl code for demultiplexer 8 to 1 using 4 to 1 vhdl code for demultiplexer for 1 to 8 using 1 to 4 vhdl code lte remote rf RRUS
    Text: OBSAI v1.1 DS612 August 8, 2007 Product Specification Introduction LogiCORE Facts The LogiCORE OBSAI core implements an OBSAI RP3 interface supporting RP3-01 at 768 MB, 1.5 Gbps, and 3 Gbps per second using RocketIO™ GTP Transceivers available for Virtex™-5 FPGAs. The OBSAI core


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    PDF DS612 RP3-01 g/getieee802/) vhdl code for demultiplexer RRUS 01 BBU RRU free source code for cdma transceiver using vhdl obsai vhdl code for demultiplexer 8 to 1 using 4 to 1 vhdl code for demultiplexer for 1 to 8 using 1 to 4 vhdl code lte remote rf RRUS

    SP006

    Abstract: verilog code for pci express memory transaction ML505 h1h2 XC5VLX110T-1FF1136 UG197 h3d1 multi context FPGA XAPP869 ML523
    Text: Application Note: Virtex-5 Family Point-to-Point Connectivity Using Integrated Endpoint Block for PCI Express Designs R XAPP869 v1.0 October 4, 2007 Summary Authors: Sunita Jain and Guru Prasanna This application note provides a reference design for point-to-point (FPGA to FPGA)


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    PDF XAPP869 SP006 verilog code for pci express memory transaction ML505 h1h2 XC5VLX110T-1FF1136 UG197 h3d1 multi context FPGA XAPP869 ML523

    LXT388

    Abstract: LXT380 LXT381 LXT384 LXT386 249143 Intel LXT384
    Text: product brief Intel LXT384 Octal T1/E1/J1 Line Interface Unit Intel Delivers Intel Advantage With the introduction of its LXT38x series, Intel offers a transceiver that supports G.772 nonintrusive performance monitoring. This feature allows one channel to eavesdrop on other


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    PDF LXT384 LXT38x LXT384 USA/0501/3K/ASI/DC LXT388 LXT380 LXT381 LXT386 249143 Intel LXT384

    3g call flow

    Abstract: XAPP1014 vhdl code for multiplexing table dvb-t SMPTE 296M timing 720p30 smpte 424m to smpte 274m hd-SDI deserializer LVDS 20k preset variable resistor vhdl code for multiplexing Tables in dvb-t ML571 verilog code for interpolation filter
    Text: Audio/Video Connectivity Solutions for Virtex-5 FPGAs Reference Designs for the the Broadcast Industry: Volume 2 Broadcast Industry: Volume 2 [optional] XAPP1014 v1.0 April 29, 2009 [optional] Xilinx is disclosing this user guide, manual, release note, and/or specification (the "Documentation") to you solely for use in the development


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    PDF XAPP1014 3g call flow XAPP1014 vhdl code for multiplexing table dvb-t SMPTE 296M timing 720p30 smpte 424m to smpte 274m hd-SDI deserializer LVDS 20k preset variable resistor vhdl code for multiplexing Tables in dvb-t ML571 verilog code for interpolation filter

    eglxt973c

    Abstract: EGLXT973 LXT973 A3 EGLXT973C A3 EGLXT973QCA3V LXT973 SLXT973QE.A3V SLXT973QEA3V LXT973QC eglxt973qe.a3v
    Text: Cortina Systems LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver Specification Update 20 March 2007 Document Number 249737 Revision 10.0 *Other names and brands may be claimed as the property of others. Cortina Systems, Inc. 2001−2007 LXT973 PHY Transceiver


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    PDF LXT973 eglxt973c EGLXT973 LXT973 A3 EGLXT973C A3 EGLXT973QCA3V SLXT973QE.A3V SLXT973QEA3V LXT973QC eglxt973qe.a3v

    B5589-01

    Abstract: UCLXT312E b5589 LXT315ANE LXT312ANE PDLXT312ANE.A2 INTEL LOT NUMBER code label LXT315ANE-A2 PDLXT315ANE PDLXT315ANE.A2
    Text: Intel LXT312A/LXT315A Low Power T1 PCM Repeaters/Transceivers Datasheet The LXT312A and LXT315A are integrated repeater/transceiver circuits for T1 carrier systems. The LXT312A is a dual repeater/transceiver and the LXT315A is a single repeater/transceiver.


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    PDF LXT312A/LXT315A LXT312A LXT315A B5589-01 B5589-01 UCLXT312E b5589 LXT315ANE LXT312ANE PDLXT312ANE.A2 INTEL LOT NUMBER code label LXT315ANE-A2 PDLXT315ANE PDLXT315ANE.A2

    Untitled

    Abstract: No abstract text available
    Text: Advance Information TMU3113MS USB Full Speed Controller Data Sheet Tenx reserves the right to change or discontinue this product without notice. tenx technology inc. tenx technology, inc. Preliminary Rev 1.0, 2010/03/30 TMU3113MS USB Full Speed controller


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    PDF TMU3113MS 130mA,

    XAPP1014

    Abstract: smpte 424m to smpte 274m 3G-SDI serializer XAPP224 DATA RECOVERY 425M SMPTE-305M PCIe BT.656 ML571 vhdl code for multiplexing Tables in dvb-t SONY service manual circuits
    Text: Audio/Video Connectivity Solutions for Virtex-5 FPGAs Reference Designs for the Broadcast Industry: Volume 2 XAPP1014 v1.2 November 9, 2009 Xilinx is disclosing this user guide, manual, release note, and/or specification (the "Documentation") to you solely for use in the development


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    PDF XAPP1014 XAPP1014 smpte 424m to smpte 274m 3G-SDI serializer XAPP224 DATA RECOVERY 425M SMPTE-305M PCIe BT.656 ML571 vhdl code for multiplexing Tables in dvb-t SONY service manual circuits

    WJLXT971ALE.A4

    Abstract: WJLXT972ALC.A4 WJLXT971ALC.A4 WJ972MA4 ELLXT971 ELLXT971ABE WJLXT971 ELLXT971ABE.A4 ELLXT971C ELLXT971ABEA4
    Text: Cortina Systems LXT971A, LXT972A, LXT972M Single-Port 10/100 Mbps PHY Transceivers Specification Update 15 March 2007 Document Number 249354 Revision 13.0 *Other names and brands may be claimed as the property of others. Cortina Systems, Inc. 1999−2007


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    PDF LXT971A, LXT972A, LXT972M LXT97x B5311-01 WJLXT971ALE.A4 WJLXT972ALC.A4 WJLXT971ALC.A4 WJ972MA4 ELLXT971 ELLXT971ABE WJLXT971 ELLXT971ABE.A4 ELLXT971C ELLXT971ABEA4

    ericsson BTS and antenna installation

    Abstract: HUAWEI Base Station bts huawei IEEE1588 phy ericsson bts maintenance BTS NSN Huawei LTE IP clock* huawei HUAWEi antenna ericsson bts operation and maintenance
    Text: Communications Infrastructure November 2008 Jay Canteenwala Kurt Rentel Panelists • Jay Canteenwala – Business Marketing Manager • Kurt Rentel – Director - Fort Collins Development Center • Tom Floyd – Moderator 2 Objectives • Develop an understanding of market trends in the


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    adaptive algorithm dpd

    Abstract: virtex GTH xilinx digital Pre-distortion DSP48E1 SX475T FPGA Virtex 6 Ethernet Virtex 6 3G-SDI serializer 6.25G interlaken network processor
    Text: FPGA FAMILY virtex-6 FPGAs Th e H ig h-Pe r for mance Prog ram mab le Si licon Fou n dation for Targ ete d Desig n Platfor ms Satisfying the Insatiable Demand for Higher Bandwidth The Programmable Imperative The High-Performance Silicon Foundation • Competitive forces are driving


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    ABBA

    Abstract: LXT6051QE 9922H AU-AIS LXT6051 VC12 SLXT6051 LXT6251 W117
    Text: Datasheet JUNE 1999 Revision 2.0 LXT6051 STM-1/0 SDH Overhead Terminator General Description Features The LXT6051 Overhead Terminator implements the Regenerator Section Termination, Multiplexer Section Termination and Higher Order Path Termination in STM-0


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    PDF LXT6051 LXT6051 51Mb/s) 155Mb/s) LXT6251 ABBA LXT6051QE 9922H AU-AIS VC12 SLXT6051 LXT6251 W117

    DESIGN AND IMPLEMENTATION 16-BIT BARREL SHIFTER

    Abstract: verilog code for barrel shifter kcpsm3 picoblaze kcpsm3 verilog code for 64 bit barrel shifter ML525 barrel shifter using verilog IMPLEMENTATION of 4-BIT LEFT SHIFT BARREL SHIFTER SFI-5 DS202
    Text: Application Note: Virtex-5 FPGAs R SERDES Framer Interface Level 5 Author: Ralf Krueger XAPP871 v1.0 February 28, 2008 Summary This application note describes the implementation of SERDES Framer Interface Level 5 (SFI-5) in a Virtex-5 XC5VLX330T FPGA. SFI-5 is a standard defined by the Optical


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    PDF XAPP871 XC5VLX330T DESIGN AND IMPLEMENTATION 16-BIT BARREL SHIFTER verilog code for barrel shifter kcpsm3 picoblaze kcpsm3 verilog code for 64 bit barrel shifter ML525 barrel shifter using verilog IMPLEMENTATION of 4-BIT LEFT SHIFT BARREL SHIFTER SFI-5 DS202

    WJLXT905LC.C2

    Abstract: B536 LXT905LC lxt905pc WJLXT905LE.C2 document number 248991 LXT905PC.C2 EELXT905PC 248991 lxt905le c2
    Text: Intel LXT905 Universal 10BASE-T Transceiver with 3.3 V Support Datasheet The Intel® LXT905 Universal 10BASE-T Transceiver is designed for IEEE 802.3 physical layer applications. It provides, in a single CMOS device, all of the active circuitry for interfacing most


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    PDF LXT905 10BASE-T 10BASE-T 10BASE- B5361-01 WJLXT905LC.C2 B536 LXT905LC lxt905pc WJLXT905LE.C2 document number 248991 LXT905PC.C2 EELXT905PC 248991 lxt905le c2

    SLXT915QC

    Abstract: LXT915QC EGLXT915QC SLXT915QC.B3 LXT915 TG54-1006N2 unmanaged repeater PT4116 BGA PACKAGE TOP MARK intel slxt915
    Text: Intel LXT915 Simple Quad Ethernet Repeater Datasheet The Intel® LXT915 Simple Quad Ethernet Repeater is an integrated multi-port repeater designed for mixed-media networks. It provides all the active circuitry required for the repeater function in a single CMOS device. It includes one Attachment Unit Interface AUI port and four


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    PDF LXT915 10BASE-T 10BASE-2, 10BASE-5, B5436-01 SLXT915QC LXT915QC EGLXT915QC SLXT915QC.B3 TG54-1006N2 unmanaged repeater PT4116 BGA PACKAGE TOP MARK intel slxt915

    hc49r

    Abstract: No abstract text available
    Text: APRIL, 1996 DATA SHEET LXT304A Low-Power T1/E1 Short-Haul Transceiver with Receive JA The LX T 3 0 4 A is a fully integrated low-power transceiver for both North American 1.544 Mbps T 1 , and International Low power consumption (400 m W maximum) 409c less than the LXT300


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    PDF LXT304A DS-T304A-0696-5K hc49r

    021B2

    Abstract: 021b202 16 line to 4 line coder multiplexer C-03
    Text: preliminary information standard product June 1989 LXT135 TCM Integrated Quad Transceiver General Description The LXT135 is a fully integrated quad transceiver for high­ speed data transmission over unshielded twisted-pair sub­ scriber loops. The device transmits at 148kbps line rate 384


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    PDF LXT135 LXT135 PDS-T135-0689 021B2 021b202 16 line to 4 line coder multiplexer C-03