LXT6251A
Abstract: LXT6051 LXT6234 LXT6282 muldex G703 LXT380 TU12 6251A LXT625
Text: product brief Intel LXT6282 Digital Interface Product Description The Intel® LXT6282 digital interface is the telecommunication industry’s first octal E1 digital interface. It is the only solution to simultaneously address the widespread problems of jitter, wander,
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LXT6282
USA/1100/1K/MG/DC
LXT6251A
LXT6051
LXT6234
muldex
G703
LXT380
TU12
6251A
LXT625
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LXT6234
Abstract: LXT6282 E1 HDB3
Text: Data Sheet MARCH 1999 Revision 2.0 LXT6282 Octal E1 Digital Interface with CRC-4 Monitoring and Jitter/Wander Suppression General Description Features LXT6282 is an eight-channel E1 digital interface. It integrates an E1 dejitter phase locked loop, an E1 retiming
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LXT6282
LXT6282
SXT6251
PDS-6282-R1
LXT6234
E1 HDB3
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LXT6282
Abstract: LDB6282 2X32 LXT380 R112 ADPLL TG29-1505NX ,ADPLL conn 2X5
Text: LDB6282 Evaluation Board for LXT6282 and LXT380 Developer Manual January 2001 As of January 15, 2001, this document replaces the Level One document LDB6282 Evaluation Board for LXT6282 and LXT380 User Guide. Order Number: 249306-001 Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual
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LDB6282
LXT6282
LXT380
LXT380
2X32
R112
ADPLL
TG29-1505NX
,ADPLL
conn 2X5
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RT4 RR3
Abstract: T2D 78 LXT6282 mtc6 T2D 17 67 T2D 79 diode T2D 53 T2D 07 BNC-4 T2D 83 diode
Text: LXT6282 LXT380 ANALOG INTERFACE POWER SUPPLY & CLOCKS TCLK0 TPOS0 TNEG0 EXT_2.048MHz EXT_2.048MHz J9 BNC4 TCLK1 TPOS1 TNEG1 INT_2.048_REF INT_2.048_REF /RESET /RESET /RESET TCLK2 TPOS2 TNEG2 GND DPLLCKREF DPLLCKREF EXT_65.536MHz EXT_65.536MHz SEL_2.048_REF
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LXT6282
LXT380
048MHz
536MHz
74LVX08M
8-Jul-1999
RT4 RR3
T2D 78
LXT6282
mtc6
T2D 17 67
T2D 79 diode
T2D 53
T2D 07
BNC-4
T2D 83 diode
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LXT6282
Abstract: JP15 adpll intel pdh e2 74AC04 motorola LXT6251A quad 74HC04 NOT GATE datasheet STM-1 JP16 LXT334
Text: LDB6x51 Evaluation Board for LXT6051, LXT6251A, and LXT6282 Developer Manual January 2001 As of January 15, 2001, this document replaces the Level One document LDB6x51 Evaluation Board for LXT6051, LXT6251, and LXT6282 User Guide. Order Number: 249305-001
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LDB6x51
LXT6051,
LXT6251A,
LXT6282
LXT6251,
LXT6282
LXT334QFP
LXT6251A
JP15
adpll
intel pdh e2
74AC04 motorola
LXT6251A
quad 74HC04 NOT GATE datasheet
STM-1
JP16
LXT334
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nrz to hdb3
Abstract: LXT6282 E1 HDB3 249279 HDB3 to nrz intel datasheets for i9 microwave radio transmitter surface mount counter G704 LXT334
Text: LXT6282 Octal E1 Digital Interface with CRC-4 Monitoring and Jitter/Wander Suppression Datasheet LXT6282 is an eight-channel E1 digital interface. It integrates an E1 dejitter phase locked loop, an E1 retiming function and a CRC-4 monitor function for each E1 transmitter and a CRC-4
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LXT6282
LXT6282
LXT6251A
144-pin
nrz to hdb3
E1 HDB3
249279
HDB3 to nrz
intel datasheets for i9
microwave radio transmitter
surface mount counter
G704
LXT334
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40-pin male connector
Abstract: AMCC errata LXT6251A LXT6282 40 pin connector 40 PIN MALE CONNECTOR BNC connector led optical transceiver datasheet STM 1 STM-1 LXT334
Text: LDB6111 STM-1 Optical Board for use with the LDB6x51A Developer Manual January 2001 As of January 15, 2001, this document replaces the Level One document LDB6111 STM-1 Optical Board for use with the LDB6x51A User Guide. Order Number: 249308-001 Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual
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LDB6111
LDB6x51A
LDB6x51A
LDB6x51
LXT6282
LXT6251A
LXT6051
LXT334
S3032
40-pin male connector
AMCC errata
LXT6251A
LXT6282
40 pin connector
40 PIN MALE CONNECTOR
BNC connector led
optical transceiver datasheet STM 1
STM-1
LXT334
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LXT6282
Abstract: DTD17 MTC11 MTC15 header 3x2 LXT6251A intel C96 74HC04 LXT344 25X2
Text: POWER.SCH POWER SUPPLIES MHICLK MHICLK J3 EXTCLKA EXTCLKA MHBCLK MHBCLK BNC-4 LXT6051.SCH J4 EXTCLKB MRESET EXTCLKB ALTSOH.sch BNC-4 MRESET MRESET J5 EXTCLKC MRESET EXTCLKC TSYNCCLKM TSYNCCLKM BNC-4 FPGA FOR SERIAL ACCESS TSYNCCLKM LXT6051A ORDERWIR.SCH TROWM
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LXT6051
LXT6051A
LDB6X51A
21-Dec-2000
LXT6282
DTD17
MTC11
MTC15
header 3x2
LXT6251A
intel C96
74HC04
LXT344
25X2
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X1HB
Abstract: MTC13 LXT625 131-G W J 50
Text: DATA SHEET JUNE 1999 Revision 2.0 LXT6251 21 E1 SDH Mapper LXT General Description Features The LXT6251 21E1 Mapper performs asynchronous mapping and demapping of 21 E1 PDH signals into SDH. The PDH side interfaces with E1 LIUs and framers via NRZ Clock & Data, while the SDH side uses a standard
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LXT6251
VC-12
VC-12s,
PDS-6251-8/99-2
X1HB
MTC13
LXT625
131-G W J 50
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g803
Abstract: LXT6282 LXT380 multiplexing demultiplexing in microcontroller LEVEL ONE COMMUNICATIONS intel pdh E1 frame
Text: Jitter and Wander In SONET/SDH Systems White Paper January 2001 Order Number: 249347-001 As of January 15, 2001, this document replaces the Level One document Jitter and Wander In SONET/SDH Systems White Paper. Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual
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LXT6282
g803
LXT380
multiplexing demultiplexing in microcontroller
LEVEL ONE COMMUNICATIONS
intel pdh
E1 frame
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X1HB
Abstract: telecom bus DM9000 application Digital Alarm Clock by using ttl LXT6251A 001H LXT6051 MTD10 LXT6282 MTC11
Text: LXT6251A 21 E1 SDH Mapper Datasheet The LXT6251A 21E1 Mapper performs asynchronous mapping and demapping of 21 E1 PDH signals into SDH. The PDH side interfaces with E1 LIUs and framers via NRZ Clock & Data, while the SDH side uses a standard Telecom bus interface. Further processing by the companion
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LXT6251A
LXT6251A
LXT6051
X1HB
telecom bus
DM9000 application
Digital Alarm Clock by using ttl
001H
MTD10
LXT6282
MTC11
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Untitled
Abstract: No abstract text available
Text: Data Sheet LXT6282 MARCH 1999 Revision 2.0 Octal E1 Digital Interface with CRC-4 Monitoring and Jitter/Wander Suppression General Description Features LXT6282 is an eight-channel E l digital interface. It inte grates an E l dejitter phase locked loop, an E l retiming
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LXT6282
LXT6282
SXT6251
SXT6282LE.
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dtc12
Abstract: No abstract text available
Text: DATA SHEET JUNE 1999 Revision 2.0 LXT6251 21 E1 SDH Mapper General Description Features The LXT6251 21E1 Mapper performs asynchronous mapping and demapping of 21 E l PDH signals into SDH. The PDH side interfaces with E l LIUs and framers via NRZ Clock & Data, while the SDH side uses a standard
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LXT6251
LXT6251
LXT6051
VC-12
dtc12
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