Abstract: SM48C
Text: APP 2 2 1993 S C S -1H 0 M S 0 N 5 7 IIL iM M û Ê S . M 48C 1002 CMOS PROCESSOR MANAGER WITH 2K BYTES OF ZEROPOWER SRAM WITH LATCHED ADDRESS INTEGRATED LOW POWER SRAM, PROCES SOR MANAGER and POWER FAIL CONTROL CIRCUIT CONVENTIONAL SRAM OPERATION ALLOW