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    MASTER SLAVE CLOCK Search Results

    MASTER SLAVE CLOCK Result Highlights (5)

    Part ECAD Model Manufacturer Description Download Buy
    TB67S539FTG Toshiba Electronic Devices & Storage Corporation Stepping Motor Driver/Bipolar Type/Vout(V)=40/Iout(A)=2/Clock Interface Visit Toshiba Electronic Devices & Storage Corporation
    TB67S149AFTG Toshiba Electronic Devices & Storage Corporation Stepping Motor Driver/Unipolar Type/Vout(V)=84/Iout(A)=3/Clock Interface Visit Toshiba Electronic Devices & Storage Corporation
    TB67S549FTG Toshiba Electronic Devices & Storage Corporation Stepping Motor Driver/Bipolar Type/Vout(V)=40/Iout(A)=1.5/Clock Interface Visit Toshiba Electronic Devices & Storage Corporation
    TB67S589FTG Toshiba Electronic Devices & Storage Corporation Stepping Motor Driver / Bipolar Type / Vout(V)=50 / Iout(A)=3.0 / CLK input type / VQFN32 Visit Toshiba Electronic Devices & Storage Corporation
    TB67S589FNG Toshiba Electronic Devices & Storage Corporation Stepping Motor Driver / Bipolar Type / Vout(V)=50 / Iout(A)=3.0 / CLK input type / HTSSOP28 Visit Toshiba Electronic Devices & Storage Corporation

    MASTER SLAVE CLOCK Datasheets Context Search

    Catalog Datasheet MFG & Type PDF Document Tags

    marking t92

    Abstract: Marking T92 6 PIN TR
    Text: MC10186 Hex D Master-Slave Flip-Flop with Reset The MC10186 contains six high–speed, master slave type “D” flip–flops. Clocking is common to all six flip–flops. Data is entered into the master when the clock is low. Master to slave data transfer


    Original     		PDF MC10186 marking t92 Marking T92 6 PIN TR

    MC10186

    Abstract: MC10186FN MC10186L MC10186P
    Text: MC10186 Hex D Master-Slave Flip-Flop with Reset The MC10186 contains six high–speed, master slave type “D” flip–flops. Clocking is common to all six flip–flops. Data is entered into the master when the clock is low. Master to slave data transfer


    Original     		PDF MC10186 MC10186 r14525 MC10186/D MC10186FN MC10186L MC10186P

    megafunction

    Abstract: EP3SE50 EP3C40-6 EP2C35-6
    Text: Run-time programmable master or slave mode operation SPI_MS Serial Peripheral Interface Master/Slave Altera Megafunction High bit rates Bit rates generated in Master mode: ÷2, ÷4, ÷8, ÷10, ÷12, …, ÷512 of the system clock Bit rates supported in slave


    Original     		PDF EP2C35-6 EP3C40-6 EP1S20-5 EP2S60-3 EP3SE50-2 megafunction EP3SE50 EP3C40-6 EP2C35-6

    MC10176L

    Abstract: No abstract text available
    Text: MC10176 Hex D Master/Slave Flip-Flop The MC10176 contains six high-speed, master slave type “D” flip-flops. Clocking is common to all six flip-flops. Data is entered into the master when the clock is low. Master to slave data transfer takes place on the positive-going Clock transition. Thus, outputs may


    Original     		PDF MC10176 MC10176P MC10176L

    MC10176

    Abstract: 2T922 MC10176FN MC10176L MC10176P T92 marking
    Text: MC10176 Hex D Master/Slave Flip-Flop The MC10176 contains six high-speed, master slave type “D” flip-flops. Clocking is common to all six flip-flops. Data is entered into the master when the clock is low. Master to slave data transfer takes place on the positive-going Clock transition. Thus, outputs may


    Original     		PDF MC10176 MC10176 r14525 MC10176/D 2T922 MC10176FN MC10176L MC10176P T92 marking

    64x18 synchronous sram

    Abstract: TSMC Flash interface VHDL code for slave SPI with FPGA TSMC embedded Flash rx data path interface in vhdl verilog code for slave SPI with FPGA TSMC Flash memory 0.18
    Text: Run-time programmable master or slave mode operation SPI_MS Serial Peripheral Interface Master/Slave Core High bit rates Bit rates generated in Master mode: ÷2, ÷4, ÷8, ÷10, ÷12, …, ÷512 of the system clock Bit rates supported in slave mode: fSCK ≤ fSYSCLK ÷4


    Original     		PDF 16-bit 64x18 2x64x18 64x18 synchronous sram TSMC Flash interface VHDL code for slave SPI with FPGA TSMC embedded Flash rx data path interface in vhdl verilog code for slave SPI with FPGA TSMC Flash memory 0.18

    verilog code for slave SPI with FPGA

    Abstract: XC3S50 XC2V80
    Text: Run-time programmable master or slave mode operation SPI_MS Serial Peripheral Interface Master/Slave Xilinx Core High bit rates Bit rates generated in Master mode: ÷2, ÷4, ÷8, ÷10, ÷12, …, ÷512 of the system clock Bit rates supported in slave mode: fSCK ≤ fSYSCLK ÷4


    Original     		PDF 64x18 XC3S50-5 XC3S100E-5 XC2V80-6 XC4VLX15-12 XC5VLX30-3 verilog code for slave SPI with FPGA XC3S50 XC2V80

    DL122

    Abstract: MC10186
    Text: MOTOROLA SEMICONDUCTOR TECHNICAL DATA Hex D Master-Slave Flip-Flop With Reset MC10186 The MC10186 contains six high–speed, master slave type “D” flip–flops. Clocking is common to all six flip–flops. Data is entered into the master when the clock is low. Master to slave data transfer takes place on the positive–going


    Original     		PDF MC10186 MC10186 64ture DL122 MC10186/D* MC10186/D

    Untitled

    Abstract: No abstract text available
    Text: Atlantic Interface June 2002, ver. 3.0 Functional Specification 13 Features • ■ ■ ■ ■ ■ ■ Functional Description The direction of data flow on the AtlanticTM interface can be either from master to slave master source or slave to master (slave source).


    Original     		PDF

    87LPC764

    Abstract: AN430 AN435 AN463 AN464 app abstract 87LCP764
    Text: INTEGRATED CIRCUITS ABSTRACT Presents short and simple I2C software routines that support only slave rather than master or master & slave operation and an ASM demonstration program. The slave-only software in this app note complements the master mode software presented in AN464, Using


    Original     		PDF AN464, 87LPC76X AN463 87LPC76X 87LPC764 AN430 AN435 AN463 AN464 app abstract 87LCP764

    ST P239

    Abstract: 714 p180 verilog code for pci express memory transaction P181 Japan P135 equivalent 714 p181 XC000E HQ240 XC4013EPQ160 XC4013
    Text: PCI Master Interface, PCI Slave Interface February, 1997 Product Description Features • Fully 2.1 PCI compliant 32 bit, 33MHz PCI Interface ◊ Master Initiator/Target , LC-DI-PCIM-C ◊ Slave (Target-only), LC-DI-PCIS-C PCI Master and Slave Interfaces V1.1.0


    Original     		PDF 33MHz XC000E ST P239 714 p180 verilog code for pci express memory transaction P181 Japan P135 equivalent 714 p181 HQ240 XC4013EPQ160 XC4013

    Untitled

    Abstract: No abstract text available
    Text: QLUX2108-PT280C Device Data Sheet • • • • • • Utopia Level 2 Slave to Utopia Level 1 Master Bridge 1.0 Utopia Level 2/1 Bridge Core Features • Implements an Utopia L2 Slave and Utopia L1 Master providing a solution to bridge Utopia Level 1 Slave devices to a Level 2 Master


    Original     		PDF QLUX2108-PT280C af-phy-0039 af-phy-0017 50MHz 400Mbps 25MHz 200Mbps

    Untitled

    Abstract: No abstract text available
    Text: QLUX2108-PQ208C Device Data Sheet • • • • • • Utopia Level 2 Slave to Utopia Level 1 Master Bridge 1.0 Utopia Level 2/1 Bridge Core Features • Implements an Utopia L2 Slave and Utopia L1 Master providing a solution to bridge Utopia Level 1 Slave devices to a Level 2 Master


    Original     		PDF QLUX2108-PQ208C af-phy-0039 af-phy-0017 50MHz 400Mbps 25MHz 200Mbps

    Elcom Technologies

    Abstract: No abstract text available
    Text: Synthesized Clock Frequency Translator Series Features Input / Output frequency up to 155.52 / 662.08 / 2488.32 MHz Ultra Low Jitter Generation < 0.25 ps RMS Flat Jitter Transition (< 0.05 dB) LOS Indicator Master and Slave Modes Smooth Transition from Master to Slave


    Original     		PDF

    SN74ACT2440

    Abstract: SN74BCT2420
    Text: SN74ACT2440 NuBus INTERFACE CONTROLLER SCHS010 – D3158, OCTOBER 1988 – REVISED JANUARY 1991 • • • • • • • Designed for NuBus Interface Applications Supports Master, Slave, and Master/Slave Applications Conforms to ANSI/IEEE Std 1196-1987


    Original     		PDF SN74ACT2440 SCHS010 D3158, SN74BCT2420 SN74ALS2442 SN74ACT2440 SN74BCT2420

    tc4027

    Abstract: No abstract text available
    Text: TC4027BP/BF TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic TC4027BP,TC4027BF TC4027B Dual J-K Master-Slave Flip Flop TC4027B is J-K master-slave flip-flop having RESET and SET functions. In the case of J-K made, when the clock input is given with


    Original     		PDF TC4027BP/BF TC4027BP TC4027BF TC4027B TC4027BP DIP16-P-300-2 OP16-P-300-hout tc4027

    AVR32105

    Abstract: AP7000 AVR32 AVR32101 STK1000
    Text: AVR32105: Master and Slave SPI Driver Features - Four chip selects with external decoder support allow communication with up to 15 peripherals - Four chip select registers allowing up to four different slave setups in master mode - Supports a wide range of devices


    Original     		PDF AVR32105: 16-bit 2017A-AVR32-05/06 AVR32105 AP7000 AVR32 AVR32101 STK1000

    SN74BCT2420

    Abstract: SN74ACT2440
    Text: SN74ACT2440 NuBus INTERFACE CONTROLLER SCHS010 – D3158, OCTOBER 1988 – REVISED JANUARY 1991 • • • • • • • Designed for NuBus Interface Applications Supports Master, Slave, and Master/Slave Applications Conforms to ANSI/IEEE Std 1196-1987


    Original     		PDF SN74ACT2440 SCHS010 D3158, SN74BCT2420 SN74ALS2442 SN74BCT2420 SN74ACT2440

    Untitled

    Abstract: No abstract text available
    Text: Ph ilips Sem iconductors l2C slave routines for the 83C751 AN433 Author: Greg Goodhue Presents short and simple l2C software routines that support only slave rather than master or master & slave operation and an A S M demonstration program. The slave-only software in this app note complements the master


    OCR Scan     		PDF 83C751 AN433 8XC751 AN434 AN435 8XC552, 8XC562, 8XC652, 8XC654,

    SP16F70

    Abstract: No abstract text available
    Text: A F L E S S E Y W Solid State — - SP16F70 MASTER/SLAVE The SP16F70 is a D-type Master-Slave Flip-Flop designed for use in high speed digital applications. Master-slave construction renders the SP16F70 relatively insensitive to the shape of the clock waveform, since only the voltage levels at


    OCR Scan     		PDF SP16F70 SP16F70

    TRANSISTOR tr4

    Abstract: SP1670 SP1670DG SP1670LC TR23 LC20 TR22
    Text: A FLESSEY W S e m ic o n d u c to rs SP1670 MASTER/SLAVE TYPE D FLIP-FLOP The SP1670 is a D-type Master-Slave Flip-Flop designed for use in high speed digital applications. Master-slave construction renders the SP1670 relatively insensitive to the shape o f the clock waveform, since only the voltage levels at


    OCR Scan     		PDF SP1670 SP1670 TRANSISTOR tr4 SP1670DG SP1670LC TR23 LC20 TR22

    saa 1070

    Abstract: No abstract text available
    Text: M M O T O R O L A Military 10586 Hex “D” Master-Slave Flip-Flop with Reset ELECTRICALLY TESTED PER: 5962-8779301 The 10586 contains six high-speed, master slave type “D" flip-flops. Clocking is common to all six flip-flops. Data is entered into the master when the clock is


    OCR Scan     		PDF 2015DR2 saa 1070

    2sa 1303

    Abstract: SMD IC ts 3202 BUX 0715
    Text: M M O T O R O L A Military 10576 Hex “D” Master-Slave Flip-Flop ELECTRICALLY TESTED PER: JM 38510/06103 MP0 mini The 10576 contains six high-speed, master slave type “ D" flip-flops. Clocking is common to all six flip-flops. Data is entered into the master when the clock is


    OCR Scan     		PDF

    M 8824

    Abstract: m8824 8821 8824 S8824 NS8822 2S H25 88822 D 8821 N8S24
    Text: S IG N E T IC S P R E LIM IN A R Y SPECIFICATIONS DGL I N T E G R A T E D C I RC UI T S 8821 DUAL MASTER-SLAVE J-K BINARY 8822 DUAL MASTER-SLAVE J-K BINARY 8824 DUAL MASTER-SLAVE J-K BINARY The 8821, 8822 a n d 8824 D u a l M aster-Slave J-K B inaries provide pin configuration a n d logic input


    OCR Scan     		PDF 8824R M 8824 m8824 8821 8824 S8824 NS8822 2S H25 88822 D 8821 N8S24