KEIL
Abstract: No abstract text available
Text: PSoC Creator Component Datasheet I2C Master/Multi-Master/Slave 3.30 Features • Industry-standard NXP® I2C bus interface • Supports slave, master, multi-master and multi-master-slave operation Requires only two pins SDA and SCL to interface to I2C bus
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Abstract: No abstract text available
Text: PSoC Creator Component Datasheet I2C Master/Multi-Master/Slave 3.10 Features • Industry-standard NXP® I2C bus interface • Supports slave, master, multi-master and multi-master-slave operation Requires only two pins SDA and SCL to interface to I2C bus
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Untitled
Abstract: No abstract text available
Text: PSoC Creator Component Datasheet I2C Master/Multi-Master/Slave 3.0 Features • Industry-standard NXP® I2C bus interface • Supports Slave, Master, Multi-Master and Multi-Master-Slave operation Only two pins SDA and SCL required to interface to I2C bus
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Abstract: No abstract text available
Text: PSoC Creator Component Datasheet I2C Master/Multi-Master/Slave 3.20 Features • Industry-standard NXP® I2C bus interface • Supports slave, master, multi-master and multi-master-slave operation Requires only two pins SDA and SCL to interface to I2C bus
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Abstract: No abstract text available
Text: PSoC Creator Component Datasheet I2C Master/Multi-Master/Slave 3.1 Features • Industry-standard NXP® I2C bus interface • Supports slave, master, multi-master and multi-master-slave operation Requires only two pins SDA and SCL to interface to I2C bus
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Untitled
Abstract: No abstract text available
Text: PSoC Creator Component Datasheet I2C Master/Multi-Master/Slave 2.20 Features • Industry standard Philips® I2C bus interface • Supports Slave, Master, Multi-Master and Multi-Master-Slave operation Only two pins SDA and SCL required to interface to I 2C bus
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RNW RESISTOR
Abstract: arbitrage verilog code for I2C MASTER
Text: PSoC Creator Component Data Sheet I2C Master/Multi-Master/Slave 2.10 Features • Industry standard Philips® I2C bus interface • Supports Slave, Master, Multi-Master and Multi-Master-Slave operation • Only two pins SDA and SCL required to interface to I2C bus
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megafunction
Abstract: EP3SE50 EP3C40-6 EP2C35-6
Text: Run-time programmable master or slave mode operation SPI_MS Serial Peripheral Interface Master/Slave Altera Megafunction High bit rates Bit rates generated in Master mode: ÷2, ÷4, ÷8, ÷10, ÷12, …, ÷512 of the system clock Bit rates supported in slave
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EP2C35-6
EP3C40-6
EP1S20-5
EP2S60-3
EP3SE50-2
megafunction
EP3SE50
EP3C40-6
EP2C35-6
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87LCP764
Abstract: BCXA i2c software program master slave communication 87LPC764 AN430 AN435 AN463 AN464 87LPC76X
Text: INTEGRATED CIRCUITS ABSTRACT Presents short and simple I2C software routines that support only slave rather than master or master & slave operation and an ASM demonstration program. The slave-only software in this app note complements the master mode software presented in AN464, Using
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AN464,
87LPC76X
AN463
87LPC76X
87LCP764
BCXA
i2c software program
master slave communication
87LPC764
AN430
AN435
AN463
AN464
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87LPC764
Abstract: AN430 AN435 AN463 AN464 app abstract 87LCP764
Text: INTEGRATED CIRCUITS ABSTRACT Presents short and simple I2C software routines that support only slave rather than master or master & slave operation and an ASM demonstration program. The slave-only software in this app note complements the master mode software presented in AN464, Using
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AN464,
87LPC76X
AN463
87LPC76X
87LPC764
AN430
AN435
AN463
AN464
app abstract
87LCP764
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64x18 synchronous sram
Abstract: TSMC Flash interface VHDL code for slave SPI with FPGA TSMC embedded Flash rx data path interface in vhdl verilog code for slave SPI with FPGA TSMC Flash memory 0.18
Text: Run-time programmable master or slave mode operation SPI_MS Serial Peripheral Interface Master/Slave Core High bit rates Bit rates generated in Master mode: ÷2, ÷4, ÷8, ÷10, ÷12, …, ÷512 of the system clock Bit rates supported in slave mode: fSCK ≤ fSYSCLK ÷4
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16-bit
64x18
2x64x18
64x18 synchronous sram
TSMC Flash interface
VHDL code for slave SPI with FPGA
TSMC embedded Flash
rx data path interface in vhdl
verilog code for slave SPI with FPGA
TSMC Flash memory 0.18
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verilog code for slave SPI with FPGA
Abstract: XC3S50 XC2V80
Text: Run-time programmable master or slave mode operation SPI_MS Serial Peripheral Interface Master/Slave Xilinx Core High bit rates Bit rates generated in Master mode: ÷2, ÷4, ÷8, ÷10, ÷12, …, ÷512 of the system clock Bit rates supported in slave mode: fSCK ≤ fSYSCLK ÷4
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64x18
XC3S50-5
XC3S100E-5
XC2V80-6
XC4VLX15-12
XC5VLX30-3
verilog code for slave SPI with FPGA
XC3S50
XC2V80
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i2c master verilog code
Abstract: verilog code for i2c
Text: PSoC Creator Component Data Sheet I2C Master/Multi-Master/Slave 2.0 Features • Industry standard Philips® I2C bus compatible interface • Supports Slave, Master, and Multi-Master operation • Only two pins sda and scl required to interface to I2C bus
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TN261
Abstract: No abstract text available
Text: TN261 The Slave Port Driver The Rabbit family of microprocessors has hardware for a slave port, allowing a master controller to read and write certain internal registers on the Rabbit. The library, Slaveport.lib, implements a complete master/slave protocol for the Rabbit slave port. Sample libraries, Master_serial.lib and
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TN261
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AVR32105
Abstract: AP7000 AVR32 AVR32101 STK1000
Text: AVR32105: Master and Slave SPI Driver Features - Four chip selects with external decoder support allow communication with up to 15 peripherals - Four chip select registers allowing up to four different slave setups in master mode - Supports a wide range of devices
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16-bit
2017A-AVR32-05/06
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AP7000
AVR32
AVR32101
STK1000
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Untitled
Abstract: No abstract text available
Text: DeviceNet Slave / Modbus Master Gateway GW-7243D The GW-7243D is one of DeviceNet products in ICP DAS and it stands as a DeviceNet slave to Modbus TCP/RTU/ASCII master gateway device. It allows a master located on a DeviceNet network to enter a dialogue with slave devices on the Modbus TCP/RTU/ASCII network. In DeviceNet network, it
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GW-7243D
10/100Base-TX
RJ-45
122mm
GW-7243D-G
GW-7243D-G
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AVR32105
Abstract: spi slave AVR32 STK1000 Spirea Atmel AVR32 AVR32101 SPI DRIVER AP7000 AVR32
Text: AVR32105: Master and Slave SPI Driver Features - Four chip selects with external decoder support allow communication with up to 15 peripherals - Four chip select registers allowing up to four different slave setups in master mode - Supports a wide range of devices
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AVR32105:
16-bit
2017A-AVR32-05/06
AVR32105
spi slave AVR32
STK1000
Spirea
Atmel AVR32
AVR32101
SPI DRIVER
AP7000
AVR32
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master-slave 8051
Abstract: LF30CV SST25VF010 SST25VF020 F2051 FLASHFLEX51 memory chip microcontroller schematic
Text: FlashFlex51 Microcontroller Single Master, Multi-Slave Serial Peripheral Interface Application Note June 2003 FlashFlex51 MCU: Single Master, Multi-Slave Serial Peripheral Interface 1.0 INTRODUCTION 2.0 HARDWARE The SPI protocol is a widely accepted and easily used
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FlashFlex51
0000h
S72051-01-000
master-slave 8051
LF30CV
SST25VF010
SST25VF020
F2051
memory chip
microcontroller schematic
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Untitled
Abstract: No abstract text available
Text: PCI 9060SD MAY 1996 VERSION 0.6 PCI Bus Master Interface Chip for Master and Slave Adapters General Description _ Featu res_ • • PCI Specification 2.1 compliant PCI Bus Master Interface supporting master and slave adapters
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9060SD
PCI9060SD
9060SD.
hflSS14^
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transistor BC 550
Abstract: TRANSISTOR tr4 SP1670LC
Text: SP1670 MASTER/SLAVE TYPE D FLIP-FLOP The SP1670 is a D-type Master-Slave Flip-Flop designed for use in high speed digital applications. Master-slave construction renders the SP1670 relatively insensitive to the shape o f the clock waveform, since only the voltage levels at
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SP1670
SP1670
transistor BC 550
TRANSISTOR tr4
SP1670LC
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SP16F70
Abstract: No abstract text available
Text: SP16F70 SP16F70 MASTER/SLAVE D TYPE FLIP-FLOP The SP16F70 is a D-type Master-Slave Flip-Flop designed for use in high speed digital applications. Master-slave construction renders the SP16F70 relatively insensitive to the shape of the clock waveform, since only the voltage levels at
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SP16F70
SP16F70
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Untitled
Abstract: No abstract text available
Text: A PLESSEY W Solid State — SP16F70 MASTER/SLAVE The SP16F70 is a D-type Master-Slave Flip-Flop designed for use in high speed digital applications. Master-slave construction renders the SP16F70 relatively insensitive to the shape of the clock waveform, since only the voltage levels at
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SP16F70
SP16F70
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TR26
Abstract: SP16F
Text: PLESSEY SEMICONDUCTORS TS dË J 7S5GS13 DD0b7flfl □ 95D 06788 7220513 PLESSEY SEMICONDUCTORS D T 'f t '0 7 'ô J r PLESSEY S em ico n d u cto rs. SP1670 MASTER/SLAVE TYPE D FLIP-FLOP The SP1670 is a D-type Master-Slave Flip-Flop designed for use in high speed digital applications. Master-slave
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7S5GS13
SP1670
SP1670
TR25r
TR26
SP16F
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TRANSISTOR tr4
Abstract: SP1670 SP1670DG SP1670LC TR23 LC20 TR22
Text: A FLESSEY W S e m ic o n d u c to rs SP1670 MASTER/SLAVE TYPE D FLIP-FLOP The SP1670 is a D-type Master-Slave Flip-Flop designed for use in high speed digital applications. Master-slave construction renders the SP1670 relatively insensitive to the shape o f the clock waveform, since only the voltage levels at
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SP1670
SP1670
TRANSISTOR tr4
SP1670DG
SP1670LC
TR23
LC20
TR22
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