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    MATLAB SOURCE Search Results

    MATLAB SOURCE Result Highlights (5)

    Part ECAD Model Manufacturer Description Download Buy
    AD-SYNCHRONA14-EBZ Analog Devices System Source Clock Controller Visit Analog Devices Buy
    ADF4002BCPZ Analog Devices Low Frequency PLL Clock Source Visit Analog Devices Buy
    LT1118CS8-5#PBF Analog Devices L IQ, L Drop, 800mA, Source & Visit Analog Devices Buy
    LT1118CS8-5#TRPBF Analog Devices L IQ, L Drop, 800mA, Source & Visit Analog Devices Buy
    ADF4002BRUZ-RL7 Analog Devices sow Frequency PLL Clock Source Visit Analog Devices Buy

    MATLAB SOURCE Datasheets Context Search

    Catalog Datasheet MFG & Type PDF Document Tags

    cxa FM radio

    Abstract: matlab N9030A MXA agilent N6171A 5989-9377EN N9010A N9010 AGILENT 9030A 5989-4942EN
    Text: Agilent N6171A MATLAB Data Analysis Software for X-Series and PSA Series Signal and Spectrum Analyzers Technical Overview • Enhance your Agilent signal and spectrum analyzers with the data analysis power of MATLAB software Create and execute your own analysis routines and


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    PDF N6171A 5989-9723EN cxa FM radio matlab N9030A MXA agilent 5989-9377EN N9010A N9010 AGILENT 9030A 5989-4942EN

    matlab

    Abstract: DSO80000A Butterworth N5430A 5989-7819EN DSO80000B DSO90000 E2688A E2699A N5400A
    Text: Agilent N5430A Infiniium User-Defined Function Application for Infiniium Oscilloscopes Data Sheet • Enhance your Infiniium oscilloscope with the analysis power of MATLAB software • Develop custom analysis functions directly on Infiniium oscilloscopes


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    PDF N5430A 5989-5632EN matlab DSO80000A Butterworth 5989-7819EN DSO80000B DSO90000 E2688A E2699A N5400A

    Untitled

    Abstract: No abstract text available
    Text: Agilent N8806A User Defined Function for Editing and Execution for Infiniium Oscilloscopes Data Sheet • Create your own custom functions or modify included functions using the power of MATLAB software • Enables Infiniium oscilloscopes to execute customized math and


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    PDF N8806A wishe29 5990-9174EN

    fir filter design using vhdl

    Abstract: farrow FIR filter matlaB simulink design AN-347-1 VHDL for decimation filter FIR filter matlaB design Resampler sample rate converter AN3471
    Text: Farrow-Based Decimating Sample Rate Converter Application Note AN-347-1.0 Introduction The Farrow-based decimating sample rate converter demonstrates a Farrow resampler. The converter is supplied with the Altera DSP Builder version 2.2.0. You can simulate its performance in MATLAB, change it as


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    PDF AN-347-1 fir filter design using vhdl farrow FIR filter matlaB simulink design VHDL for decimation filter FIR filter matlaB design Resampler sample rate converter AN3471

    Untitled

    Abstract: No abstract text available
    Text: TravelScope DSO • PC-based, USB2.0 interface / powered • 2 channels stackable to 12 channels • 1 GS/s sampling, 200 MHz bandwidth • Export data to WORD, EXCEL, TEXT, HTML, MATLAB etc. • Trigger Group I : Edge, External, Width, Video / TV • Trigger Group II : A-B, Delay, Pattern, Runt, Setup / Hold, State, Timeout,


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    PDF TS2202E TS2212E TS2212A TS2212H TS2202E/TS2212E/TS2212A:

    st pl001

    Abstract: AN3138 matlab STEVAL-MKI062V1 MEMS pressure sensor MATLAB inemo pl001 accelerometer magnetometer pressure sensor MATLAB STM32F103Rx
    Text: AN3138 Application note Wrapper in MATLAB for the STEVAL-MKI062V1 Introduction This application note provides information on the use of the application programming interface API of the iNEMO software development kit (SDK), which provides easy-to-use function calls to obtain data from the sensors or to change settings. The dynamic link library


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    PDF AN3138 STEVAL-MKI062V1 STEVAL-MKI062V1) st pl001 AN3138 matlab STEVAL-MKI062V1 MEMS pressure sensor MATLAB inemo pl001 accelerometer magnetometer pressure sensor MATLAB STM32F103Rx

    FPGA XC6VSX315T-FF1156

    Abstract: fir compiler xilinx ff1136 ff1156 xc6vsx315t-ff1156 xc5vsx50t FIR filter matlaB simulink design simulink based program design for implementation FIR Filter matlab system generator matlab ise
    Text: Application Note: All Virtex and Spartan FPGA Families Source Control and Team-Based Design in System Generator XAPP498 v1.0 January 15, 2010 Summary Author: Douang Phanthavong This application note provides an overview on how to perform source version control and


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    PDF XAPP498 FPGA XC6VSX315T-FF1156 fir compiler xilinx ff1136 ff1156 xc6vsx315t-ff1156 xc5vsx50t FIR filter matlaB simulink design simulink based program design for implementation FIR Filter matlab system generator matlab ise

    64 point FFT radix-4 VHDL documentation

    Abstract: matlab code for half adder FSK matlab CORDIC to generate sine wave fpga simulink 3 phase inverter vhdl code for ofdm verilog code for fir filter using DA fft algorithm verilog 16-point radix-4 advantages vhdl code for radix-4 fft lfsr galois
    Text: DSP Guide for FPGAs Lattice Semiconductor Corporation 5555 NE Moore Court Hillsboro, OR 97124 503 268-8000 September 2009 Copyright Copyright 2009 Lattice Semiconductor Corporation. This document may not, in whole or part, be copied, photocopied, reproduced, translated, or reduced to any electronic medium or machinereadable form without prior written consent from Lattice Semiconductor


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    EP2C35

    Abstract: EP2S180 Blockset
    Text: DSP Builder Release Notes Release Notes June 2007, Version 7.1 SP1 These release notes for the DSP Builder software, v7.1 SP1 contain the following information: • ■ ■ ■ ■ ■ ■ ■ System Requirements System Requirements New Features & Enhancements


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    PDF R2006a, R2006b, R2007a 32-bit EP2C35 EP2S180 Blockset

    DSP processor latest version in 2010

    Abstract: r2008b vhdl code for FFT 32 point jpeg encoder vhdl code matlab multimedia projects based on matlab fpga based Numerically Controlled Oscillator dsp processor design using vhdl filter design software design filter matlaB software design
    Text: DSP Builder Handbook Volume 1: Introduction to DSP Builder 101 Innovation Drive San Jose, CA 95134 www.altera.com HB_DSPB_INTRO-1.0 Document Version: Document Date: 1.0 July 2010 Copyright 2010 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other


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    adc matlab code

    Abstract: matlaB HP16517A AN3495 HP16500C APP3495 MAX1121 MAX1122 MAX1123 MAX1124
    Text: Maxim > App Notes > BASESTATIONS / WIRELESS INFRASTRUCTURE HIGH-SPEED SIGNAL PROCESSING DIGITAL POTENTIOMETERS Keywords: integral nonlinearity, differential nonlinearity, INL, DNL, analog-to-digital converter, ADC, converter, data record, logic analyzer, data capture, concatenate


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    PDF MAX1121: MAX1122: MAX1123: MAX1124: MAX1213: MAX19541: MAX19542: AN3495, APP3495, Appnote3495, adc matlab code matlaB HP16517A AN3495 HP16500C APP3495 MAX1121 MAX1122 MAX1123 MAX1124

    Untitled

    Abstract: No abstract text available
    Text: System Generator for DSP Getting Started Guide UG639 v 14.3 October 16, 2012 This document applies to the following software versions: ISE Design Suite 14.3 through 14.6 Xilinx is disclosing this user guide, manual, release note, and/or specification (the "Documentation") to you solely for use in the development


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    PDF UG639

    multimedia projects based on matlab

    Abstract: fixed point matlab system generator matlab ise matlab code for FFT 32 point FFT CODING BY VERILOG FOR 8 POINT WITH RADIX 2 E-SYN-0002 XtremeDSP Solution
    Text: AccelDSP Synthesis Tool User Guide Release 10.1.1 April, 2008 R R Xilinx is disclosing this Document and Intellectual Property hereinafter “the Design” to you for use in the development of designs to operate on, or interface with Xilinx FPGAs. Except as stated herein, none of the Design may be copied, reproduced, distributed, republished,


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    PDF -DIR-0013 -DIR-0015 -DIR-0016 -DIR-5001 -MAT-0008 -MAT-0301 -QOR-0400 -QTZ-0006 -QTZ-0010 -QTZ-0011 multimedia projects based on matlab fixed point matlab system generator matlab ise matlab code for FFT 32 point FFT CODING BY VERILOG FOR 8 POINT WITH RADIX 2 E-SYN-0002 XtremeDSP Solution

    UG639

    Abstract: No abstract text available
    Text: System Generator for DSP Getting Started Guide UG639 v 13.1 March 1, 2011 Xilinx is disclosing this user guide, manual, release note, and/or specification (the "Documentation") to you solely for use in the development of designs to operate with Xilinx hardware devices. You may not reproduce, distribute, republish, download, display, post, or transmit the


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    PDF UG639 UG639

    matlab code using 64 point radix 8

    Abstract: radix-2 1345-2 radix fht 100
    Text: HammerCores by Altera White Paper Hadamard Transform Processor Introduction ® The Hammercores by Altera Hadamard Transform Processor core is optimized for the Altera FLEX 10KE, ACEX 1K, and APEX 20K device families. The core is parameterizable and can support a wide range of transform


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    matlab code for n point DFT using fft

    Abstract: matlab code using 8 point DFT butterfly fft matlab code using 16 point DFT butterfly fft matlab code using 8 point DFT butterfly vhdl code for dFT 32 point vhdl code for FFT 32 point matlab code for FFT 32 point fft dft MATLAB tcl script ModelSim fixed point implementation matlab
    Text: DFT/IDFT Reference Design Application Note 464 May 2007, version 1.0 Introduction The DFT reference design performs a discrete Fourier transform DFT or an inverse DFT (IDFT) of a complex input sequence and produces a complex output sequence. The reference design performs the functions for either a DFT in the uplink


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    PDF R1-062852, 46bis, matlab code for n point DFT using fft matlab code using 8 point DFT butterfly fft matlab code using 16 point DFT butterfly fft matlab code using 8 point DFT butterfly vhdl code for dFT 32 point vhdl code for FFT 32 point matlab code for FFT 32 point fft dft MATLAB tcl script ModelSim fixed point implementation matlab

    AT 2005B

    Abstract: AT 2005B at 2005b
    Text: DSP Builder Release Notes Release Notes April 2006, Version 6.0 SP1 These release notes for DSP Builder version 6.0 SP1 contain the following information: • ■ ■ ■ ■ ■ ■ ■ System Requirements System Requirements New Features & Enhancements Errata Fixed in This Release


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    PDF 2000/XP AT 2005B AT 2005B at 2005b

    verilog code for cordic algorithm

    Abstract: cordic algorithm code in verilog FIR filter design using cordic algorithm CORDIC adaptive algorithm dpd verilog code for dpd verilog code for cordic altera CORDIC ip verilog code for half subtractor verilog code for cordic algorithm for wireless
    Text: Digital Predistortion Reference Design Application Note AN-314-1.0 Introduction Power amplifiers PAs for for third-generation (3G) wireless communication systems need high linearity at the PA output, to achieve high adjacent channel leakage ratio (ACLR) and low error vector


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    PDF AN-314-1 verilog code for cordic algorithm cordic algorithm code in verilog FIR filter design using cordic algorithm CORDIC adaptive algorithm dpd verilog code for dpd verilog code for cordic altera CORDIC ip verilog code for half subtractor verilog code for cordic algorithm for wireless

    A3PE1500-PQ208

    Abstract: 341a
    Text: Synplify DSP AE Design Flow Quickstart and Design Tutorial Actel Corporation, Mountain View, CA 94043 2006 Actel Corporation. All rights reserved. Printed in the United States of America Part Number: 50200083-2 Release: November 2007 No part of this document may be copied or reproduced in any form or by any means without prior written


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    Untitled

    Abstract: No abstract text available
    Text: Agilent E1432A, E1433B, E1434A VXI Digitizers/Source Product Overview A high-performance system architecture for demanding mechanical, acoustic and electrical data acquisition applications. ● Agilent E1432A 16-channel 51.2 kSa/sec/chan Digitzer plus DSP


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    PDF E1432A, E1433B, E1434A E1432A 16-channel E1433B E1432A

    AT 2005B

    Abstract: AT 2005B at 2005b EP2C35 EP2S180
    Text: DSP Builder Release Notes Release Notes March 2007, Version 7.0 These release notes for DSP Builder version 7.0 contain the following information: • ■ ■ ■ ■ ■ ■ ■ System Requirements System Requirements New Features & Enhancements Errata Fixed in This Release


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    PDF 2000/XP AT 2005B AT 2005B at 2005b EP2C35 EP2S180

    AT 2005B

    Abstract: AT 2005B at 2005B EP2C35 EP2S180
    Text: DSP Builder Release Notes Release Notes December 2006, Version 6.1 These release notes for DSP Builder version 6.1 contain the following information: • ■ ■ ■ ■ ■ ■ ■ System Requirements System Requirements New Features & Enhancements Errata Fixed in This Release


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    PDF 2000/XP AT 2005B AT 2005B at 2005B EP2C35 EP2S180

    LMS matlab

    Abstract: FIR filter matlaB design LMS adaptive filter matlab matlab OIF2003 SDD21 fir filter design ifft transmitter
    Text: Studies on FIR Filter Pre-Emphasis for High-Speed Backplane Data Transmission Miao Li Department of Electronics Carleton University Ottawa, ON. K1S5B6, Canada Tel: 613 5205754 Email:mili@doe.carleton.ca Yuming Tao Ottawa IC Development ALTERA Corp. Ottawa, ON. K2K3C9 Canada


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    PDF 5-10Gbs 25-um OIF2003 LMS matlab FIR filter matlaB design LMS adaptive filter matlab matlab SDD21 fir filter design ifft transmitter

    verilog for Twiddle factor

    Abstract: verilog for 8 point fft Radix-3 FFT verilog for 16 point fft fft algorithm verilog an4801 verilog radix 2 fft fft dft MATLAB radix-2 fft verilog dit fft algorithm verilog
    Text: 1536-Point FFT for 3GPP Long Term Evolution Application Note 480 October 2007, ver. 1.0 Introduction 3GPP Long Term Evolution LTE is an ongoing project to improve the universal mobile telecommunication system (UMTS) standard to handle future requirements of mobile phones. The main targets include higher


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    PDF 1536-Point verilog for Twiddle factor verilog for 8 point fft Radix-3 FFT verilog for 16 point fft fft algorithm verilog an4801 verilog radix 2 fft fft dft MATLAB radix-2 fft verilog dit fft algorithm verilog