MEGAFUNCTIONS Search Results

MEGAFUNCTIONS Datasheets (80)

Part	Manufacturer	Description	Datasheet Type	PDF
Megafunctions: Communications	Altera	ATM Cell Processor 622 Mbps MegaCore Function (CP622) User Guide	Original	PDF
Megafunctions: Communications	Altera	Utopia Level 2 Slave MegaCore Function User Guide	Original	PDF
Megafunctions: Communications	Altera	SONET STS-1 Framer MegaCore Function (STS1FRM) User Guide	Original	PDF
Megafunctions: Communications	Altera	Turbo Encoder-Decoder MegaCore Function User Guide	Original	PDF
Megafunctions: Communications	Altera	Utopia Level 2 Master MegaCore Function User Guide	Original	PDF
Megafunctions: Communications	Altera	Viterbi Compiler MegaCore Function User Guide	Original	PDF
Megafunctions: Communications	Altera	ATM Cell Processor 155 Mbps MegaCore Function (CP155) User Guide	Original	PDF
Megafunctions: Communications	Altera	SONET-SDH STS-3c-STM-1 Framer MegaCore Function (STS3CFRM) User Guide	Original	PDF
Megafunctions: Communications	Altera	SONET STS-3 Framer MegaCore Function (STS1X3FRM) User Guide	Original	PDF
Megafunctions: Communications	Altera	FS 8: Midbus Interface Specification	Original	PDF
Megafunctions: Communications	Altera	POS-PHY Level 2 & 3 Compiler MegaCore Functions User Guide	Original	PDF
Megafunctions: Communications	Altera	PPP Packet Processor 155 Mbps MegaCore Function (PP155) User Guide	Original	PDF
Megafunctions: Communications	Altera	FS 9: AIRbus Interface Specification	Original	PDF
Megafunctions: Communications	Altera	FS 13: Atlantic Interface	Original	PDF

Megafunctions: Communications	Altera	Reed-Solomon Compiler MegaCore Function User Guide	Original	PDF
Megafunctions: Communications	Altera	PPP Packet Processor 622 Mbps MegaCore Function (PP622) User Guide	Original	PDF
Megafunctions: Communications	Altera	T3 Framer MegaCore Function (T3FRM) User Guide	Original	PDF
Megafunctions: Communications	Altera	SONET-SDH STS-12c-STM-4 Framer MegaCore Function (STS12CFRM) User Guide	Original	PDF
Megafunctions: Communications	Altera	AN 141: T3 Framer MegaCore Function--Implementing Loopback Functions	Original	PDF
Megafunctions: Communications	Altera	T3 Mapper MegaCore Function (T3MSP)	Original	PDF

MEGAFUNCTIONS Datasheets Context Search

Catalog Datasheet	Type	Document Tags	PDF
rc5 protocol Abstract: EP2C5T144C6 RC5 encoder RC5 philips RC5 IR philips RC5 decoder philips RC5 protocol altera manchester RC5 decoder EP1C3T100C6 Text:  5-bit address and 6-bit com- mand length IR-RC5-E and -D Infrared Encoder and Decoder Megafunctions  Bi-phase coding also known as Manchester coding  Carrier frequency of 36 kHz as per the RC5 standard  Fully synchronous design Encoder Features	Original		PDF
EPF10K100B Abstract: EPF10K100E EPF10K130E EPF10K200E EPF10K30E EPF10K50E EPF10K50S Text: FLEX 10KE Embedded Programmable Logic Devices March 2001, ver. 2.3 Data Sheet • Features. ■ ■ f Embedded programmable logic devices PLDs , providing system-on-a-programmable-chip (SOPC) integration in a single device – Enhanced embedded array for implementing megafunctions	Original	16-bit EPF10K100B EPF10K100E EPF10K130E EPF10K200E EPF10K30E EPF10K50E EPF10K50S	PDF
EPF10K50S Abstract: EPF10K100B EPF10K100E EPF10K130E EPF10K200E EPF10K30E EPF10K50E FLEX controller vhdl code Text: FLEX 10KE Embedded Programmable Logic Family September 2000, ver. 2.10 Features. Data Sheet • ■ ■ f Embedded programmable logic devices PLDs , providing system-on-a-programmable-chip integration in a single device – Enhanced embedded array for implementing megafunctions	Original	16-bit EPF10K50S EPF10K100B EPF10K100E EPF10K130E EPF10K200E EPF10K30E EPF10K50E FLEX controller vhdl code	PDF
Untitled Abstract: No abstract text available Text: Implementing Fractional PLL Reconfiguration with Altera PLL and Altera PLL Reconfig Megafunctions AN-661-3.0 Application Note This application note describes the flow for implementing fractional phase-locked loop PLL reconfiguration and dynamic phase shifting for fractional PLLs in 28-nm	Original	AN-661-3 28-nm 28-nm	PDF
HDTV transmitter receivers block diagram Abstract: 20 channel GRAPHIC EQUALIZER eureka pci 64 10 channel GRAPHIC EQUALIZER block diagram graphic equalizer image processing DSP asic sican dsp adsl typical "bit error rate" MPEG-4 decoder receiver ADSL Modem circuit diagram Text: ¨ Megafunctions Selector Guide System-on-a-Programmable-Chip Solutions June 1999 Contents 2 Introduction to Altera Megafunctions 4 Digital Signal Processing Megafunctions 7 Communications Megafunctions 8 PCI & Other Bus Interface Megafunctions 10 Processor & Peripheral Megafunctions	Original	M-SG-MEGAFCTN-02 HDTV transmitter receivers block diagram 20 channel GRAPHIC EQUALIZER eureka pci 64 10 channel GRAPHIC EQUALIZER block diagram graphic equalizer image processing DSP asic sican dsp adsl typical "bit error rate" MPEG-4 decoder receiver ADSL Modem circuit diagram	PDF
alt_iobuf Abstract: ep3*SL150F1152C2 altera double data rate megafunction sdc UG-01032-4 Text: ALTDLL and ALTDQ_DQS Megafunctions User Guide 101 Innovation Drive San Jose, CA 95134 www.altera.com Software Version: Document Version: Document Date: 9.1 4.0 May 2010 Copyright 2010 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other	Original		PDF
Untitled Abstract: No abstract text available Text: Evaluating AMPP & MegaCore Functions April 2001, ver. 2.0 Introduction Application Note 125 Altera and Altera Megafunction Partners Program AMPPSM partners offer a large selection of off-the-shelf megafunctions optimized for Altera devices. Designers can easily implement these parameterized blocks of	Original		PDF
T flip flop CMOS IC Abstract: blf 188 Text: FLEX10KE Embedded Programmable Logic Family May 1999» ver.2 Data Sheet $§ Features. Preliminary Information ^ Embedded programmable logic devices PLDs , providing System-on-a-Programmable-Chip integration in a single device Enhanced embedded array for implementing megafunctions	OCR Scan	FLEX10KE 16-bit 256-Pin 484-P 672-Pin EPF10K30E EPF10K50E EPF10K50S EPF10K100 T flip flop CMOS IC blf 188	PDF
AXP 209 IC Abstract: orcad schematic symbols library Text: FLEX 10K Embedded Programmable Logic Family October 199B, ver. 3.13 Features. •. Data Sheet ^ 88 The industry's first embedded programmable logic device PLD family, providing system integration in a single device Embedded array for implementing megafunctions, such as	OCR Scan		PDF
dcfifo Abstract: asynchronous fifo vhdl altera MTBF dcfifo_mixed_widths Text: SCFIFO and DCFIFO Megafunctions UG-MFNALT_FIFO-6.2 User Guide Altera provides FIFO functions through the parameterizable single-clock FIFO SCFIFO and dual-clock FIFO (DCFIFO) megafunctions. The FIFO functions are mostly applied in data buffering applications that comply with the first-in-first-out	Original		PDF
EPF10K130eqc240 Abstract: EPF10K200SFI epf10k50eqc208 EPF10K50EFC484-1 EPF10K50EFC484-3 epf10k50sfc EPF10K50SFC484-3 epf10k30etc144-3 Text: FLEX 10KE Embedded Programmable Logic Devices March 2001, ver. 2.3 Data Sheet • Features. ■ ■ f Embedded programmable logic devices PLDs , providing system-on-a-programmable-chip (SOPC) integration in a single device – Enhanced embedded array for implementing megafunctions	Original	16-bit /EPF10K200S EPF10K130eqc240 EPF10K200SFI epf10k50eqc208 EPF10K50EFC484-1 EPF10K50EFC484-3 epf10k50sfc EPF10K50SFC484-3 epf10k30etc144-3	PDF
implementation of 8-tap fir filter vhdl Abstract: uart verilog code Text: FLEX 10KE Embedded Programmable Logic Family June 1999, ver. 2.01 Features. Data Sheet • Preliminary Information ■ ■ f Embedded programmable logic devices PLDs , providing System-on-a-Programmable-ChipTM integration in a single device – Enhanced embedded array for implementing megafunctions	Original	16-bit 484-pin 356-pin EPF10K50E EPF10K50S implementation of 8-tap fir filter vhdl uart verilog code	PDF
EPF10K200SRC240-1X Abstract: EPF10K50SFC484-3 Text: FLEX 10KE Embedded Programmable Logic Device January 2003, ver. 2.5 Features. Data Sheet • ■ ■ f Embedded programmable logic devices PLDs , providing system-on-a-programmable-chip (SOPC) integration in a single device – Enhanced embedded array for implementing megafunctions	Original	16-bit PF10K50EQC240-2 EPF10K50EQC240-3 EPF10K50EQI240-2 EPF10K50ETC144-1 EPF10K50ETC144-2 EPF10K50ETC144-3 EPF10K50ETI144-2 EPF10K50E EPF10K200SRC240-1X EPF10K50SFC484-3	PDF
Untitled Abstract: No abstract text available Text: FLEX 10K Embedded Programmable Logic Family Data Sheet May 1998. ver. 3.10 Features. * r*^te industry's first embedded programmable logic device PLD H B family, providing system integration in a single device Embedded array for implementing megafunctions, such as	OCR Scan		PDF

microprocessors architecture of 8251 Abstract: 8251 uart in vhdl code VHDL CODE FOR 8255 vhdl source code for fft how to test fft megacore Reed-Solomon Decoder verilog code 8251 DMA controller design of dma controller using vhdl 8259 interrupt controller vhdl code Text: Introduction to Megafunctions January 1998, ver. 1 Overview With programmable logic device PLD densities reaching 250,000 gates, it is now possible to implement entire digital subsystems on a single PLD. However, designing at higher density levels poses a new set of challenges.	Original		PDF
MegaCore IP Library Abstract: megacore ip Text: OpenCore Plus Evaluation of Megafunctions Application Note 320 November 2007, version 1.6 Introduction Altera and Altera Megafunction Partners Program AMPPSM partners offer a broad portfolio of megafunctions optimized for Altera devices. The Altera MegaCore® functions and AMPP megafunctions are reusable	Original		PDF
EPF10K50S Abstract: verilog for 8 point fft vhdl code for FFT 32 point EPF10K100B EPF10K100E EPF10K130E EPF10K200E EPF10K30E EPF10K50E Text: FLEX 10KE Embedded Programmable Logic Devices January 2001, ver. 2.2 Data Sheet • Features. ■ ■ f Embedded programmable logic devices PLDs , providing system-on-a-programmable-chip integration in a single device – Enhanced embedded array for implementing megafunctions	Original	16-bit EPF10K50S verilog for 8 point fft vhdl code for FFT 32 point EPF10K100B EPF10K100E EPF10K130E EPF10K200E EPF10K30E EPF10K50E	PDF
EPF10K50E Abstract: EPF10K50S EPF10K100B EPF10K100E EPF10K130E EPF10K200E EPF10K30E Text: FLEX 10KE Embedded Programmable Logic Device January 2003, ver. 2.5 Features. Data Sheet • ■ ■ f Embedded programmable logic devices PLDs , providing system-on-a-programmable-chip (SOPC) integration in a single device – Enhanced embedded array for implementing megafunctions	Original	16-bit EPF10K50E EPF10K50S EPF10K100B EPF10K100E EPF10K130E EPF10K200E EPF10K30E	PDF
vhdl code for 4 to 1 multiplexers quartus Abstract: 220Model QII53014-7 lpm compile Text: 5. Simulating Altera IP in Third-Party Simulation Tools QII53014-7.1.0 Introduction The capacity and complexity of Altera FPGAs continues to increase as the need for intellectual property IP becomes increasingly critical. Using IP megafunctions reduces the design and verification time, allowing you	Original	QII53014-7 vhdl code for 4 to 1 multiplexers quartus 220Model lpm compile	PDF
Untitled Abstract: No abstract text available Text: ALTCHIP_ID Megafunction 2013.09.20 ug-altchipid Subscribe Feedback You can configure the features of the ALTCHIP_ID megafunction using the MegaWizard Plug-In Manager in the Quartus II software. If you are not familiar with megafunctions and how to create them, refer to the	Original		PDF
FIR FILTER implementation in c language Abstract: PCIH IBM T21 Data Sheet data sheet of preset 10k verilog for 8 point fft MAKING A10 BGA FIR Filter verilog code bga 529 49.152 ba37 diode Text: FLEX 10KE Embedded Programmable Logic Family August 1999, ver. 2.02 Features. Data Sheet • Preliminary Information ■ ■ f Embedded programmable logic devices PLDs , providing System-on-a-Programmable-ChipTM integration in a single device – Enhanced embedded array for implementing megafunctions	Original	16-bit EPF10K200E EPF10K200S 600-pin 356-pin EPF10K50E EPF10K50S FIR FILTER implementation in c language PCIH IBM T21 Data Sheet data sheet of preset 10k verilog for 8 point fft MAKING A10 BGA FIR Filter verilog code bga 529 49.152 ba37 diode	PDF
XZ132 Abstract: F10K25 Clock Management with ClockLock & ClockBoost Features White Paper Text: FLEX 10K ,u r v Includes R JE X 10 K A Embedded Programmable Logic Family May 1999, ver. 4 Features. Data Sheet • ■ ■ The industry's first embedded programmable logic device PLD family, providing System-on-a-Programmable-Chip integration Embedded array for implementing megafunctions, such as	OCR Scan	EPF10K 600-pin XZ132 F10K25 Clock Management with ClockLock & ClockBoost Features White Paper	PDF
EIA-IS103 Abstract: two 4 bit binary multiplier Vhdl code verilog hdl code for 4 to 1 multiplexer in quartus 2 UG-01056-1 Text: Megafunction Overview User Guide February 2009 UG-01056-1.0 Introduction Megafunctions are vendor-specific intellectual property IP blocks that are parameterizable and optimized for Altera device architectures. Altera provides a library of megafunctions,	Original	UG-01056-1 EIA-IS103 two 4 bit binary multiplier Vhdl code verilog hdl code for 4 to 1 multiplexer in quartus 2	PDF
UG-MF9304-3 Abstract: EP2C5T144C6 integrated display device dual port memory cells AN550 Text: ALTDQ and ALTDQS Megafunctions User Guide UG-MF9304-3.1 November 2009 Introduction The Quartus II software provides parameterizable megafunctions ranging from simple arithmetic units, such as adders and counters, to advanced phase-locked loop PLL blocks, multipliers, and memory structures. These megafunctions are	Original	UG-MF9304-3 EP2C5T144C6 integrated display device dual port memory cells AN550	PDF

MEGAFUNCTIONS Search Results

MEGAFUNCTIONS Datasheets (80)

MEGAFUNCTIONS Datasheets Context Search

rc5 protocol

EPF10K100B

EPF10K50S

Untitled

HDTV transmitter receivers block diagram

alt_iobuf

Untitled

T flip flop CMOS IC

AXP 209 IC

dcfifo

EPF10K130eqc240

implementation of 8-tap fir filter vhdl

EPF10K200SRC240-1X

Untitled

microprocessors architecture of 8251

MegaCore IP Library

EPF10K50S

EPF10K50E

vhdl code for 4 to 1 multiplexers quartus

Untitled

FIR FILTER implementation in c language

XZ132

EIA-IS103

UG-MF9304-3