O16N
Abstract: I22P I29N O09P O26P O27P O16P O25P O31P I28P
Text: a 34 ؋ 34, 3.2 Gbps Asynchronous Digital Crosspoint Switch AD8152 FEATURES Low Cost Low Power 2.0 W @ 2.5 V Outputs Enabled <100 mW @ 2.5 V (Outputs Disabled) 34 ؋ 34, Fully Differential, Nonblocking Array 3.2 Gbps per Port NRZ Data Rate Wide Power Supply Range: 2.5 V to 3.3 V
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AD8152
256-Ball
OC-48
MO-192-BAL-2
1/03--Data
C02984
O16N
I22P
I29N
O09P
O26P
O27P
O16P
O25P
O31P
I28P
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SAA7119
Abstract: saa7154 RSN 309 W 44H SAA7154H SAA7154E SAA7118 An RTCO 7AH SPLPL9 myson mtv048 SAA7154E/V2
Text: SAA7154E; SAA7154H Multistandard video decoder with comb filter, component input and RGB output Rev. 02 — 6 December 2007 Product data sheet 1. General description The SAA7154E; SAA7154H is a high-quality multistandard video decoder supporting 10-bit Analog-to-Digital Converter ADC , enhanced PAL/NTSC comb filtering, more
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SAA7154E;
SAA7154H
SAA7154H
10-bit
24-bit
SAA7154E
SAA7119
saa7154
RSN 309 W 44H
SAA7118 An
RTCO 7AH
SPLPL9
myson mtv048
SAA7154E/V2
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LP62S2048AX-70LLTF
Abstract: 8X13 LP62S2048A-T
Text: LP62S2048A-T Series 256K X 8 BIT LOW VOLTAGE CMOS SRAM Document Title 256K X 8 BIT LOW VOLTAGE CMOS SRAM Revision History Rev. No. History Issue Date Remark 0.0 Initial issue June 24, 2002 Preliminary 0.1 Change VCC range from 2.7V~3.3V to 2.7V~3.6V October 15, 2002
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LP62S2048A-T
32-pin
MO192
LP62S2048AX-70LLTF
8X13
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TDA8275
Abstract: 7133h tda8275a SAA7131E tda18271 SAA7135 saa7131e 03 g tda18271 vsync dvb strong power supply circuit diagram nxp saa7131E
Text: SAA7131E Global standard low-IF demodulator and PCI audio and video decoder for analog TV Rev. 03 — 19 May 2008 Product data sheet 1. General description The SAA7131E combines a digital global standard low-IF demodulator for analog TV with a PCI audio and video decoder.
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SAA7131E
SAA7131E
TDA18271,
TDA8275A
TDA8275
7133h
tda18271
SAA7135
saa7131e 03 g
tda18271 vsync
dvb strong power supply circuit diagram
nxp saa7131E
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LP62E16256E
Abstract: LP62E16256E-T
Text: LP62E16256E-T Series 256K X 16 BIT LOW VOLTAGE CMOS SRAM Document Title 256K X 16 BIT LOW VOLTAGE CMOS SRAM Revision History Rev. No. History Issue Date Remark 0.0 Initial issue July 4, 2002 Preliminary 1.0 Final version release July 17, 2003 Final July, 2003, Version 1.0
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LP62E16256E-T
304-bit
MO192
LP62E16256E
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LP62S1024B
Abstract: LP62S1024BM-55LLT LP62S1024B-T
Text: LP62S1024B-T Series 128K X 8 BIT LOW VOLTAGE CMOS SRAM Document Title 128K X 8 BIT LOW VOLTAGE CMOS SRAM Revision History Rev. No. History Issue Date Remark 0.0 Initial issue February 19, 2002 Preliminary 0.1 Add 32L Pb-Free TSSOP package type October 2, 2002
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LP62S1024B-T
MO192
LP62S1024B
LP62S1024BM-55LLT
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smd transistor HB
Abstract: LP62S16128B-T
Text: LP62S16128B-T Series 128K X 16 BIT LOW VOLTAGE CMOS SRAM Features n Operating voltage: 2.7V to 3.6V n Access times: 55/70 ns max. n Current: Very low power version: Operating: 55ns 40mA (max.) 70ns 35mA (max.) Standby: 10µA (max.) n n n n n Full static operation, no clock or refreshing required
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LP62S16128B-T
44-pin
48-ball
MO192
smd transistor HB
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LP62S1024
Abstract: LP62S1024B LP62S1024B-I LP62S1024BM-55LLI LP62S1024BX-I LP62S1024BX-55LLIF CE25
Text: LP62S1024B-I Series 128K X 8 BIT LOW VOLTAGE CMOS SRAM Document Title 128K X 8 BIT LOW VOLTAGE CMOS SRAM Revision History Rev. No. History Issue Date Remark 0.0 Initial issue May 30, 2002 Preliminary 0.1 Add 32L Pb-Free TSSOP package type October 2, 2002 1.0
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LP62S1024B-I
MO192
LP62S1024
LP62S1024B
LP62S1024BM-55LLI
LP62S1024BX-I
LP62S1024BX-55LLIF
CE25
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dac interfacing with 8051 microcontroller free do
Abstract: No abstract text available
Text: 32-Channel, 14-Bit Voltage-Output DAC AD5532 FEATURES GENERAL DESCRIPTION High integration: 32-channel DAC in 12 mm x 12 mm CSPBGA Adjustable voltage output range Guaranteed monotonic Readback capability DSP/microcontroller compatible serial interface Output impedance:
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32-Channel,
14-Bit
AD5532
32-channel
AD5532-1,
AD5532-2)
AD5532-3)
AD5532-5)
AD5532-3,
dac interfacing with 8051 microcontroller free do
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ADM3252E
Abstract: ADM3252EABCZ adm3252
Text: FEATURES FUNCTIONAL BLOCK DIAGRAM C1 0.1µF 16V C3 0.1µF 10V C1+ C1– V+ ADM3252E 0.1µF VCC 10µF 2.5 kV fully isolated power and data RS-232 transceiver isoPower integrated, isolated dc-to-dc converter Operational from single 3.3 V or 5 V supply 460 kbps data rate
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RS-232
ADM3252E
EIA/TIA-232E
2-14-2010-A
MO-192-ABD-1.
44-Ball
BC-44-1)
ADM3252EABCZ
EVAL-ADM3252EEBZ
ADM3252E
adm3252
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transistor SMD BR21
Abstract: SMD Transistor W08 adsp-21369ksz smd w04 74 smd code t04 smd code W06 transistor SMD W06 sMD .v05 smd transistor w04 SMD Transistors w06 56
Text: a SHARC Processors ADSP-21367/ADSP-21368/ADSP-21369 SUMMARY Code compatible with all other members of the SHARC family The ADSP-21367/ADSP-21368/ADSP-21369 are available with a 333 MHz core instruction rate with unique audiocentric peripherals such as the digital audio interface, S/PDIF
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ADSP-21367/ADSP-21368/ADSP-21369
ADSP-21367/ADSP-21368/ADSP-21369
32-bit/40-bit
ADSP-21369KSZ-1A2
ADSP-21368BBP-2A
256-Ball
BP-256
D05267-0-8/06
transistor SMD BR21
SMD Transistor W08
adsp-21369ksz
smd w04 74
smd code t04
smd code W06
transistor SMD W06
sMD .v05
smd transistor w04
SMD Transistors w06 56
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jat52
Abstract: TA-TSY-000191 PM5319 PM5319-NI PMC-2030860
Text: us t, 20 04 09 :2 1: 24 PM ARROW 622 ASSP Telecom Standard Product Data Sheet Released es da y, 10 Au g PM5319 gi es , In c. on Tu ARROW 622 Released Issue No. 2: July 2004 Do wn lo ad ed by Sc o tt E st es of i 2T ec h no lo ASSP Telecom Standard Product Data Sheet
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PMC-2031158,
PM5319
196-pin
PM5319-NI
jat52
TA-TSY-000191
PM5319
PM5319-NI
PMC-2030860
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Diode LT 228d
Abstract: 1E2H SMD making code DV5
Text: 7: 43 AM PM4323 OCTLIU LT Device ASSP Telecom Standard Product Data Sheet Released ,0 ay co n Th ur sd OCTLIU LT 1M ay ,2 00 8 01 :0 PM4323 of Pa rtm in er In Device Telecom Standard Product Proprietary and Confidential Released Issue No. 5: April 2008 Do
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PM4323
PMC-2021612,
PM4323
PMC-2021612
MO-192,
Diode LT 228d
1E2H
SMD making code DV5
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LP62S16512-55LLI
Abstract: 0.3mm pitch BGA 0.3mm pitch csp package LP62S16512U-70LLI LP62S16512 LP62S16512-I
Text: LP62S16512-I Series Preliminary 512K X 16 BIT LOW VOLTAGE CMOS SRAM Document Title 512K X 16 BIT LOW VOLTAGE CMOS SRAM Revision History Rev. No. 0.2 PRELIMINARY History Issue Date Remark Add Product Family and 55ns specification March 20, 2002 Preliminary
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LP62S16512-I
MO192
LP62S16512-55LLI
0.3mm pitch BGA
0.3mm pitch csp package
LP62S16512U-70LLI
LP62S16512
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AD5532-2
Abstract: AD5532 AD5532-1 AD5532-3 AD5532-5 AD5532ABC-1 AD5532ABC-2 AD780 diagram of dac interfacing with 8051 SSPcon
Text: a 32-Channel, 14-Bit Voltage-Output DAC AD5532* GENERAL DESCRIPTION FEATURES High Integration: 32-Channel DAC in 12 mm ؋ 12 mm LFBGA Adjustable Voltage Output Range Guaranteed Monotonic Read-Back Capability DSP/Microcontroller Compatible Serial Interface
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32-Channel,
14-Bit
AD5532*
32-Channel
AD5532-1,
AD5532-2)
AD5532-3)
AD5532-5)
AD5532-3,
AD5532-2
AD5532
AD5532-1
AD5532-3
AD5532-5
AD5532ABC-1
AD5532ABC-2
AD780
diagram of dac interfacing with 8051
SSPcon
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ARM Cortex M4
Abstract: cortex a15 core LPC4330 ARM Cortex A8 arm cortex a9 CE-ATA version 1.1 cortex a15 cpu cortex a15 cortex-m4 cortex a9
Text: LPC4350/30/20/10 32-bit ARM Cortex-M4/M0 MCU; up to 264 kB SRAM; Ethernet; two High-speed USBs; advanced configurable peripherals Rev. 1 — 29 October 2010 Objective data sheet 1. General description The LPC4350/30/20/10 are ARM Cortex-M4 based microcontrollers for embedded
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LPC4350/30/20/10
32-bit
LPC4350/30/20/10
LPC4350
ARM Cortex M4
cortex a15 core
LPC4330
ARM Cortex A8
arm cortex a9
CE-ATA version 1.1
cortex a15 cpu
cortex a15
cortex-m4
cortex a9
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VOLTAGE DEPENDENT RESISTOR panasonic
Abstract: No abstract text available
Text: :2 5: 39 PM Octal Short-Haul E1/T1/J1 Line Interface Device Telecom Standard Product Data Sheet Released nd ay ,1 6S ep te OCTLIU-SH m be r, 20 07 10 PM4319 Data Sheet Proprietary and Confidential Released Issue No. 3: May 2002 Do wn l oa de d by I HS Pa r
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PMC-2012568,
PM4319
MO-192,
VOLTAGE DEPENDENT RESISTOR panasonic
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Untitled
Abstract: No abstract text available
Text: LP62S16128C-I Series 128K X 16 BIT LOW VOLTAGE CMOS SRAM Document Title 128K X 16 BIT LOW VOLTAGE CMOS SRAM Revision History History Issue Date Remark 0.0 Initial issue April 26, 2002 Preliminary 1.0 Change ICC2 from 15mA to 8mA May 23, 2003 Final Rev. No.
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LP62S16128C-I
152bit
MO192
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Untitled
Abstract: No abstract text available
Text: Package outline LBGA256: plastic low profile ball grid array package; 256 balls; body 17 x 17 x 1.05 mm A B D SOT740-1 ball A1 index area A E A2 A1 detail X C e1 1/2 e e ∅v M C A B b y y1 C ∅w M C T R e P N M L K J e2 H 1/2 e G F E D C B A ball A1 index area
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LBGA256:
OT740-1
MO-192
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Untitled
Abstract: No abstract text available
Text: LP62S1024B-T Series Preliminary 128K X 8 BIT LOW VOLTAGE CMOS SRAM Document Title 128K X 8 BIT LOW VOLTAGE CMOS SRAM Revision History Rev. No. 0.0 PRELIMINARY History Issue Date Remark Initial issue February 19, 2002 Preliminary February, 2002, Version 0.0
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LP62S1024B-T
MO192
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Untitled
Abstract: No abstract text available
Text: LP62E16256E-I Series 256K X 16 BIT LOW VOLTAGE CMOS SRAM Document Title 256K X 16 BIT LOW VOLTAGE CMOS SRAM Revision History Rev. No. 0.0 History Issue Date Remark Initial issue December 12, 2006 Final December, 2006, Version 0.0 AMIC Technology, Corp. LP62E16256E-I Series
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LP62E16256E-I
304bit
MO192
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310N
Abstract: 31VG
Text: REVISIONS LTR £ ^ DESCRIPTION A RELEASE B D I M ' S 1 . 3 7 + 0 . 1 WAS 1 . 46+0. 19/ 0 . 09, 0.34 ± 0 . 0 4 WAS 0 . 4 M I N , 0 0 . 4 9 ± 0 . 0 5 WAS 0 0 . 5 ; R E V I S E NOT E 4 & T I T L E . TO D O C U ME N T C O N T R O L BALL PAD 1 . 3710. 1 CORNER
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31VDS
v96igrn-i
31VDS
0608-2S0S6
261-OW
NOIlVdlSI93d
39N3d3J3d
Md3H10
SS31NÃ
S310N
310N
31VG
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SD313
Abstract: 310N
Text: REV I S IONS LTR DESCRIPTION A RELEASE TO D O C U M E N T CONTROL E.C.N. DATE 12384 02/29/2000 Al 22.86 1.27 BALL BY/APP'D TL/MJL CORNER- TYP TYP 00OOOOOOOOOOOOOOOO0 ooooooooooooooooooo ooooooooooooooooooo OOO OOO OOO OOO OOO OOO OOO OOO OOO OOO OOO OOO OOO
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133HS
VZ61VHÃ
0608-2S096
N3Wn30a
3SV313!
261-OW
IIVdlSI03<
30N3H3J3H
NO111SOdNOD
SS31NÃ
SD313
310N
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Untitled
Abstract: No abstract text available
Text: REVISIONS DESCRI PTI ON LTR & A RELEASE B D I M ' S 1 . 3 7 + 0 . 1 WAS 1 . 4 6 + 0 . 1 9 / - 0 . 0 9 , 1. 34 + 0 . 0 4 WAS 0 . 4 MI N, 0 0 . 49 ± 0 . 05 WAS 0 0 . 5 R E V I S E NOT E 4 & T I T L E . TO D O C U ME N T C O N T R O L 0 0 .1 5 N L© 00. 08©
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