mr 4020 pin assignment
Abstract: MC100E150
Text: MC10E150, MC100E150 5V ECL 6-Bit D Latch The MC10E/100E150 contains six D-type latches with differential outputs. When both Latch Enables LEN1, LEN2 are LOW, the latch is transparent and input data transitions propagate through to the output. A logic HIGH on either LEN1 or LEN2 (or both) latches the
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MC10E150,
MC100E150
MC10E/100E150
PLCC-28
AND8020
AN1404
AN1405
AN1406
AN1503
AN1504
mr 4020 pin assignment
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Untitled
Abstract: No abstract text available
Text: MC10E143, MC100E143 5V ECL 9-Bit Hold Register The MC10E/100E143 is a 9-bit holding register, designed with byte-parity applications in mind. The E143 holds current data or loads new data, with the nine inputs D0 − D8 accepting parallel input data. The SEL Select input pin is used to switch between the two modes
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MC10E143,
MC100E143
MC10E/100E143
AND8020
MC100E143
AN1404
AN1405
AN1406
AN1503
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mr 4020
Abstract: MC100E175
Text: MC10E175, MC100E175 5V ECL 9-Bit Latch With Parity The MC10E/100E175 is a 9-bit latch. It also features a tenth latched output, ODDPAR, which is formed as the odd parity of the nine data inputs ODDPAR is HIGH if an odd number of the inputs are HIGH . The E175 can also be used to generate byte parity by using D8 as the
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MC10E175,
MC100E175
MC10E/100E175
AND8020
AN1404
AN1405
AN1406
AN1503
AN1504
AN1568
mr 4020
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Untitled
Abstract: No abstract text available
Text: MC10E167, MC100E167 5V ECL 6-Bit 2:1 MUX-Register The MC10E/100E167 contains six 2:1 multiplexers followed by D flip-flops with single-ended outputs. Input data are selected by the Select control, SEL. The selected data are transferred to the flip-flop outputs by a positive edge on CLK1 or CLK2 or both . A HIGH on
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MC10E167,
MC100E167
MC10E/100E167
AND8020
AN1404
AN1405
AN1406
AN1503
AN1504
AN1568
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Untitled
Abstract: No abstract text available
Text: MC10E155, MC100E155 5V ECL 6−Bit 2:1 Mux−Latch The MC10E/100E155 contains six 2:1 multiplexers followed by transparent latches with single−ended outputs. When both Latch Enables LEN1, LEN2 are LOW, the latch is transparent, and output data is controlled by the multiplexer select control, SEL. A logic
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MC10E155,
MC100E155
MC10E/100E155
AND8020
AN1404
AN1405
AN1406
AN1503
AN1504
AN1568
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transistor phl 815
Abstract: No abstract text available
Text: MC10E141, MC100E141 5V ECL 8-Bit Shift Register The MC10E/100E141 is an 8-bit full-function shift register. The E141 performs serial/parallel in and serial/parallel out, shifting in either direction. The eight inputs D0 − D7 accept parallel input data, while
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MC10E141,
MC100E141
MC10E/100E141
AND8020
MC100E141
AN1404
AN1405
AN1406
AN1503
transistor phl 815
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Untitled
Abstract: No abstract text available
Text: MC10E154, MC100E154 5V ECL 5-Bit 2:1 Mux-Latch The MC10E/100E154 contains five 2:1 multiplexers followed by transparent latches with differential outputs. When both Latch Enables LEN1, LEN2 are LOW, the latch is transparent, and output data is controlled by the multiplexer select control, SEL. A logic HIGH on
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MC10E154,
MC100E154
MC10E/100E154
AND8020
AN1404
AN1405
AN1406
AN1503
AN1504
AN1568
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transistor Bd 575
Abstract: No abstract text available
Text: MC10E212, MC100E212 5V ECL 3-Bit Scannable Registered Address Driver The MC10E/100E212 is a scannable registered ECL driver typically used as a fan-out memory address driver for ECL cache driving. In a VLSI array based CPU design, use of the E212 allows the user to
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MC10E212,
MC100E212
MC10E/100E212
AND8020
AN1404
AN1405
AN1406
AN1503
AN1504
AN1568
transistor Bd 575
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socket 775 pinout
Abstract: mr 4030
Text: MC10E156, MC100E156 5V ECL 3-Bit 4:1 Mux-Latch The MC10E/100E156 contains three 4:1 multiplexers followed by transparent latches with differential outputs. When both Latch Enables LEN1, LEN2 are LOW, the latch is transparent, and output date is controlled by the multiplexer select controls (SEL0, SEL1). A logic
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MC10E156,
MC100E156
MC10E/100E156
AND8020
AN1404
AN1405
AN1406
AN1503
AN1504
AN1568
socket 775 pinout
mr 4030
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MC100E150
Abstract: No abstract text available
Text: MC10E150, MC100E150 5V ECL 6-Bit D Latch The MC10E/100E150 contains six D-type latches with differential outputs. When both Latch Enables LEN1, LEN2 are LOW, the latch is transparent and input data transitions propagate through to the output. A logic HIGH on either LEN1 or LEN2 (or both) latches the
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MC10E150,
MC100E150
MC10E/100E150
PLCC-28
MC10E150/D
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MC100E150
Abstract: mr 4020 MC100E150FN MC100E150FNR2 MC10E150 MC10E150FN MC10E150FNR2
Text: MC10E150, MC100E150 5VĄECL 6ĆBit D Latch The MC10E/100E150 contains six D-type latches with differential outputs. When both Latch Enables LEN1, LEN2 are LOW, the latch is transparent and input data transitions propagate through to the output. A logic HIGH on either LEN1 or LEN2 (or both) latches the
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MC10E150,
MC100E150
MC10E/100E150
MC10E150FN
r14525
MC10E150/D
MC100E150
mr 4020
MC100E150FN
MC100E150FNR2
MC10E150
MC10E150FN
MC10E150FNR2
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Untitled
Abstract: No abstract text available
Text: MC10EL34, MC100EL34 5V ECL ÷2, ÷4, ÷8 Clock Generation Chip The MC10/100EL34 is a low skew ÷2, ÷4, ÷8 clock generation chip designed explicitly for low skew clock generation applications. The internal dividers are synchronous to each other, therefore, the common
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MC10EL34,
MC100EL34
MC10/100EL34
intern00
BRD8011/D.
AN1405/D
AN1406/D
AN1503/D
AN1504/D
AN1568/D
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1005 Ic Data
Abstract: IC 4050 DATA SHEET pin diagram ic 4030 E143 MC100E143 MC100E143FN MC100E143FNR2 MC10E143 MC10E143FN MC10E143FNR2
Text: MC10E143, MC100E143 5V ECL 9-Bit Hold Register The MC10E/100E143 is a 9-bit holding register, designed with byte-parity applications in mind. The E143 holds current data or loads new data, with the nine inputs D0 − D8 accepting parallel input data. The SEL Select input pin is used to switch between the two modes
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MC10E143,
MC100E143
MC10E/100E143
MC10E143FN
MC10E143/D
1005 Ic Data
IC 4050 DATA SHEET
pin diagram ic 4030
E143
MC100E143
MC100E143FN
MC100E143FNR2
MC10E143
MC10E143FN
MC10E143FNR2
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MC100E175
Abstract: E175 MC100E175FN MC100E175FNR2 MC10E175 MC10E175FN MC10E175FNR2 E175 transistor
Text: MC10E175, MC100E175 5VĄECL 9ĆBit Latch With Parity The MC10E/100E175 is a 9-bit latch. It also features a tenth latched output, ODDPAR, which is formed as the odd parity of the nine data inputs ODDPAR is HIGH if an odd number of the inputs are HIGH . The E175 can also be used to generate byte parity by using D8 as the
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MC10E175,
MC100E175
MC10E/100E175
MC10E175FN
r14525
MC10175/D
MC100E175
E175
MC100E175FN
MC100E175FNR2
MC10E175
MC10E175FN
MC10E175FNR2
E175 transistor
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mr 4030
Abstract: mr 4020 E143 MC100E143 MC100E143FN MC100E143FNR2 MC10E143 MC10E143FN MC10E143FNR2
Text: MC10E143, MC100E143 5VĄECL 9ĆBit Hold Register The MC10E/100E143 is a 9-bit holding register, designed with byte-parity applications in mind. The E143 holds current data or loads new data, with the nine inputs D0 – D8 accepting parallel input data. The SEL Select input pin is used to switch between the two modes
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MC10E143,
MC100E143
MC10E/100E143
MC10E143FN
r14525
MC10E143/D
mr 4030
mr 4020
E143
MC100E143
MC100E143FN
MC100E143FNR2
MC10E143
MC10E143FN
MC10E143FNR2
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mr 4020
Abstract: MC100E151 MC100E151FN MC100E151FNR2 MC10E151 MC10E151FN MC10E151FNR2
Text: MC10E151, MC100E151 5VĄECL 6ĆBit D Register The MC10E/100E151 contains 6 D-type, edge-triggered, master-slave flip-flops with differential outputs. Data enters the master when both CLK1 and CLK2 are LOW, and is transferred to the slave when CLK1 or CLK2 or both go HIGH. The asynchronous
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MC10E151,
MC100E151
MC10E/100E151
MC10E151FN
r14525
MC10E151/D
mr 4020
MC100E151
MC100E151FN
MC100E151FNR2
MC10E151
MC10E151FN
MC10E151FNR2
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MC100E151
Abstract: MC100E151FN MC100E151FNR2 MC10E151 MC10E151FN MC10E151FNR2
Text: MC10E151, MC100E151 5V ECL 6-Bit D Register The MC10E/100E151 contains 6 D-type, edge-triggered, master-slave flip-flops with differential outputs. Data enters the master when both CLK1 and CLK2 are LOW, and is transferred to the slave when CLK1 or CLK2 or both go HIGH. The asynchronous
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MC10E151,
MC100E151
MC10E/100E151
MC10E151FN
MC10E151/D
MC100E151
MC100E151FN
MC100E151FNR2
MC10E151
MC10E151FN
MC10E151FNR2
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MC100E167
Abstract: 100E167 MC100E167FN MC100E167FNR2 MC10E167 MC10E167FN MC10E167FNR2
Text: MC10E167, MC100E167 5VĄECL 6ĆBit 2:1 MuxĆRegister The MC10E/100E167 contains six 2:1 multiplexers followed by D flip-flops with single-ended outputs. Input data are selected by the Select control, SEL. The selected data are transferred to the flip-flop
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MC10E167,
MC100E167
MC10E/100E167
MC10E167FN
r14525
MC10E167/D
MC100E167
100E167
MC100E167FN
MC100E167FNR2
MC10E167
MC10E167FN
MC10E167FNR2
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MC100E150
Abstract: MC100E150FN MC100E150FNR2 MC10E150 MC10E150FN MC10E150FNR2 mr 4030
Text: MC10E150, MC100E150 5VĄECL 6ĆBit D Latch The MC10E/100E150 contains six D-type latches with differential outputs. When both Latch Enables LEN1, LEN2 are LOW, the latch is transparent and input data transitions propagate through to the output. A logic HIGH on either LEN1 or LEN2 (or both) latches the
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MC10E150,
MC100E150
MC10E/100E150
MC10E150FN
75ONlit
r14525
MC10E150/D
MC100E150
MC100E150FN
MC100E150FNR2
MC10E150
MC10E150FN
MC10E150FNR2
mr 4030
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el34
Abstract: 100EL34 10EL34 MC100EL34 MC100EL34D MC100EL34DR2 MC10EL34 MC10EL34D MC10EL34DR2
Text: MC10EL34, MC100EL34 5V ECL ÷2, ÷4, ÷8 Clock Generation Chip The MC10/100EL34 is a low skew ÷2, ÷4, ÷8 clock generation chip designed explicitly for low skew clock generation applications. The internal dividers are synchronous to each other, therefore, the common
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MC10EL34,
MC100EL34
MC10/100EL34
MC10EL34/D
el34
100EL34
10EL34
MC100EL34
MC100EL34D
MC100EL34DR2
MC10EL34
MC10EL34D
MC10EL34DR2
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Untitled
Abstract: No abstract text available
Text: MC10EL34, MC100EL34 5V ECL ÷2, ÷4, ÷8 Clock Generation Chip The MC10/100EL34 is a low skew ÷2, ÷4, ÷8 clock generation chip designed explicitly for low skew clock generation applications. The internal dividers are synchronous to each other, therefore, the common
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MC10EL34,
MC100EL34
MC10/100EL34
MC10EL34/D
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MC100E167FNR2
Abstract: MC10E167 MC10E167FN MC10E167FNR2 MC100E167 MC100E167FN
Text: MC10E167, MC100E167 5V ECL 6-Bit 2:1 MUX-Register The MC10E/100E167 contains six 2:1 multiplexers followed by D flip-flops with single-ended outputs. Input data are selected by the Select control, SEL. The selected data are transferred to the flip-flop outputs by a positive edge on CLK1 or CLK2 or both . A HIGH on
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MC10E167,
MC100E167
MC10E/100E167
MC10E167/D
MC100E167FNR2
MC10E167
MC10E167FN
MC10E167FNR2
MC100E167
MC100E167FN
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MC100E151
Abstract: MC100E151FN MC100E151FNR2 MC10E151 MC10E151FN MC10E151FNR2
Text: MC10E151, MC100E151 5VĄECL 6ĆBit D Register The MC10E/100E151 contains 6 D-type, edge-triggered, master-slave flip-flops with differential outputs. Data enters the master when both CLK1 and CLK2 are LOW, and is transferred to the slave when CLK1 or CLK2 or both go HIGH. The asynchronous
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MC10E151,
MC100E151
MC10E/100E151
MC10E151FN
r14525
MC10E151/D
MC100E151
MC100E151FN
MC100E151FNR2
MC10E151
MC10E151FN
MC10E151FNR2
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MR 4010
Abstract: el34 100EL34 10EL34 MC100EL34 MC100EL34D MC100EL34DR2 MC10EL34 MC10EL34D MC10EL34DR2
Text: MC10EL34, MC100EL34 5VĄECL ÷2, ÷4, ÷8 Clock Generation Chip The MC10/100EL34 is a low skew ÷2, ÷4, ÷8 clock generation chip designed explicitly for low skew clock generation applications. The internal dividers are synchronous to each other, therefore, the common
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MC10EL34,
MC100EL34
MC10/100EL34
r14525
MC10EL34/D
MR 4010
el34
100EL34
10EL34
MC100EL34
MC100EL34D
MC100EL34DR2
MC10EL34
MC10EL34D
MC10EL34DR2
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