MRAM PCI Search Results

MRAM PCI Result Highlights (5)

Part	Manufacturer	Description
AM79C971AVC\\W	Rochester Electronics	AM79C971 - Single-Chip Full-Duplex 10/100 Mbps Ethernet Controller for PCI Local Bus
AM79C961AVC	Rochester Electronics LLC	AM79C961 - Full Duplex 10/100 MBPS ETHERNET Controller for PCI Local Bus, PCNET- ISA II jumperless
AM79C961AVI\\W	Rochester Electronics	AM79C961 - Full Duplex 10/100 MBPS ETHERNET Controller for PCI Local Bus, PCNET- ISA II jumperless
AM79C961AKC\\W-G	Rochester Electronics	AM79C961 - Full Duplex 10/100 MBPS ETHERNET Controller for PCI Local Bus, PCNET- ISA II jumperless
AM79C961AVC\\W	Rochester Electronics	AM79C961 - Full Duplex 10/100 MBPS ETHERNET Controller for PCI Local Bus, PCNET- ISA II jumperless

MRAM PCI Datasheets Context Search

Catalog Datasheet	MFG & Type	Document Tags	PDF
HC1S40 Abstract: HC1S60 Text: 10. Description, Architecture, and Features H51002-3.3 Introduction HardCopy Stratix® structured ASICs provide a comprehensive alternative to ASICs. The HardCopy Stratix device family is fully supported by the Quartus® II design software, and, combined with a vast	Original	H51002-3 HC1S40 HC1S60	PDF
HC1S60 Abstract: No abstract text available Text: 2. Description, Architecture, and Features H51002-3.4 Introduction HardCopy Stratix ® structured ASICs provide a comprehensive alternative to ASICs. The HardCopy Stratix device family is fully supported by the Quartus® II design software, and, combined with a vast	Original	H51002-3 HC1S60	PDF
circuit diagram of half adder Abstract: EP1S60 Text: 2. Stratix Architecture S51002-3.2 Functional Description Stratix devices contain a two-dimensional row- and column-based architecture to implement custom logic. A series of column and row interconnects of varying length and speed provide signal interconnects	Original	S51002-3 circuit diagram of half adder EP1S60	PDF
logic diagram to setup adder and subtractor Abstract: CLK12 1818D Text: 4. Stratix GX Architecture SGX51004-1.0 Logic Array Blocks Each LAB consists of 10 LEs, LE carry chains, LAB control signals, local interconnect, LUT chain, and register chain connection lines. The local interconnect transfers signals between LEs in the same LAB. LUT chain	Original	SGX51004-1 logic diagram to setup adder and subtractor CLK12 1818D	PDF
4046 PLL Designers Guide Abstract: EP1S60 Text: Stratix August 2002, ver. 2.1 Introduction Preliminary Information Features. Data Sheet The StratixTM family of programmable logic devices PLDs is based on a 1.5-V, 0.13-µm, all-layer copper SRAM process, with densities up to 114,140 logic elements (LEs) and up to 10 Mbits of RAM. Stratix devices	Original	420-MHz 4046 PLL Designers Guide EP1S60	PDF
IT 8572E Abstract: 8572E MRAM PCI PCI6466 CPCI-6115 PICMG 2.1 ddr3 MTBF CompactPCI Express specification IT+8572E TSI384 Text: CPCI6200 PICMG 2.0/2.16 Processor Board PRELIMINARY DATA SHEET The CPCI6200 offers high speed bandwidth and serverclass performance for compute intensive and control plane applications. nn 1.3 or 1.5 GHz Freescale MPC8572 dual core integrated processor nn Integrated north bridge in the	Original	CPCI6200 CPCI6200 MPC8572 DDR3-800 CPCI6200-D0 IT 8572E 8572E MRAM PCI PCI6466 CPCI-6115 PICMG 2.1 ddr3 MTBF CompactPCI Express specification IT+8572E TSI384	PDF
vhdl code for PLL Abstract: EP2S15 EP2S180 EP2S30 EP2S60 EP2S90 vhdl code for 4*4 crossbar switch Text: 2. Stratix II Architecture SII51002-4.3 Functional Description Stratix II devices contain a two-dimensional row- and column-based architecture to implement custom logic. A series of column and row interconnects of varying length and speed provides signal interconnects	Original	SII51002-4 vhdl code for PLL EP2S15 EP2S180 EP2S30 EP2S60 EP2S90 vhdl code for 4*4 crossbar switch	PDF
circuit diagram of full subtractor circuit Abstract: "Fast Cycle RAM" Serial RapidIO Infiniband logic diagram to setup adder and subtractor 32 bit carry select adder code HP lvds connector 40 pin to 30 pin to 7 pin infiniband Physical Medium Attachment SSTL-18 transistor on 4436 Text: Stratix GX March 2003, ver. 1.2 Introduction FPGA Family Data Sheet Preliminary Information The StratixTM GX family of devices is Altera’s second FPGA family to combine high-speed serial transceivers with a scalable, high-performance logic array. Stratix GX devices include 4 to 20 high-speed transceiver	Original		PDF
Altera Stratix V Abstract: circuit diagram of ddr ram Text: 1. Introduction to the Stratix GX Device Data Sheet SGX51001-1.0 Overview The Stratix GX family of devices is Altera’s second FPGA family to combine high-speed serial transceivers with a scalable, high-performance logic array. Stratix GX devices include 4 to 20 high-speed transceiver	Original	SGX51001-1 EP1SGX10 EP1SGX25 EP1SGX40 Altera Stratix V circuit diagram of ddr ram	PDF
74HC230 Abstract: HC210 BGA-614 EP2S180 EP2S30 EP2S60 EP2S90 HC220 HC230 HC240 Text: 8. Migrating Stratix II Device Resources to HardCopy II Devices H51024-1.4 Introduction Altera HardCopy® II devices and Stratix® II devices are both manufactured on a 1.2-V, 90-nm process technology and offer many similar features. Designers can use the Quartus® II software to migrate	Original	H51024-1 90-nm 74HC230 HC210 BGA-614 EP2S180 EP2S30 EP2S60 EP2S90 HC220 HC230 HC240	PDF
EP2S90 Abstract: HC210 Stratix II EP2S60 HC220 HC230 HC240 EP2S180 EP2S30 EP2S60 Text: 8. Migrating Stratix II Device Resources to HardCopy II Devices H51024-1.3 Introduction Altera HardCopy® II devices and Stratix® II devices are both manufactured on a 1.2-V, 90-nm process technology and offer many similar features. Designers can use the Quartus® II software to migrate	Original	H51024-1 90-nm EP2S90 HC210 Stratix II EP2S60 HC220 HC230 HC240 EP2S180 EP2S30 EP2S60	PDF
spi sata controller Abstract: MVME7216E-101 MVME2502-02120201E MVME5110 scanbe MVME2500 MVME721ET-101 RS-232 to usb circuit diagram freescale p2020 boot software SDhc socket Text: MVME2500 Series VME64 Processor Board QorIQ processor based board provides high performance at a low power envelope nn 800 MHz or 1.2G Hz Freescale QorIQ P2010 and P2020 processors nn 1GB or 2GB DDR3-800, soldered down nn Three on-board Gigabit Ethernet interfaces one front,	Original	MVME2500 VME64 P2010 P2020 DDR3-800, P2020. MVME2500-D0 spi sata controller MVME7216E-101 MVME2502-02120201E MVME5110 scanbe MVME721ET-101 RS-232 to usb circuit diagram freescale p2020 boot software SDhc socket	PDF
SSTL-18 Abstract: No abstract text available Text: Stratix GX November 2002, ver. 1.0 Introduction FPGA Family Data Sheet Preliminary Information The StratixTM GX family of devices is Altera’s second FPGA family to combine high-speed serial transceivers with a scalable, high-performance logic array. Stratix GX devices include 4 to 20 high-speed transceiver	Original		PDF
Stratix 8300 Abstract: 484-pin BGA 4008 adders EP1S60 Text: Stratix December 2002, ver. 3.0 Introduction Preliminary Information Features. Data Sheet The StratixTM family of FPGAs is based on a 1.5-V, 0.13-µm, all-layer copper SRAM process, with densities up to 114,140 logic elements LEs and up to 10 Mbits of RAM. Stratix devices offer up to 28 digital signal	Original	420-MHz Stratix 8300 484-pin BGA 4008 adders EP1S60	PDF

simple block diagram for digital clock Abstract: AGX51002-2 cascade shift register prbs generator using vhdl Text: 2. Arria GX Architecture AGX51002-2.0 Transceivers Arria GX devices incorporate up to 12 high-speed serial transceiver channels that build on the success of the Stratix ® II GX device family. Arria GX transceivers are structured into full-duplex transmitter and receiver four-channel groups called	Original	AGX51002-2 simple block diagram for digital clock cascade shift register prbs generator using vhdl	PDF
verilog sample code for max1619 Abstract: ep2s60f1020c5n EP2S60F484C4 pin diagram EP2S90F1020C3 verilog code for crossbar switch EP2S60F672I4N Text: Section I. Stratix II Device Family Data Sheet This section provides designers with the data sheet specifications for Stratix II devices. They contain feature definitions of the internal architecture, configuration and JTAG boundary-scan testing information,	Original	be2S60F1020C3N EP2S60F1020C4 EP2S60F1020C4N EP2S60F1020C5 EP2S60F1020C5N EP2S60F484I4 EP2S60F484I4N EP2S60F672I4 EP2S60F672I4N EP2S60F1020I4 verilog sample code for max1619 EP2S60F484C4 pin diagram EP2S90F1020C3 verilog code for crossbar switch	PDF
EP2S90F1020C5 Abstract: EP2S90F1020C3 Text: Section I. Stratix II Device Family Data Sheet This section provides designers with the data sheet specifications for Stratix II devices. They contain feature definitions of the internal architecture, configuration and JTAG boundary-scan testing information,	Original	EP2S30F484C3 EP2S30 EP2S30F484C4 EP2S30F484C5 EP2S30F672C3 EP2S30F672C4 EP2S30F672C5 EP2S30 EP2S90F1020C5 EP2S90F1020C3	PDF
Untitled Abstract: No abstract text available Text: Section I. Stratix Device Family Data Sheet This section provides designers with the data sheet specifications for Stratix devices. They contain feature definitions of the internal architecture, configuration and JTAG boundary-scan testing information, DC operating conditions, AC timing parameters, a reference to power	Original		PDF
"Stratix IV" Package layout information Abstract: EP1S25F780C7 EP1S30F780C7 S-51005 Text: Stratix Device Handbook, Volume 1 101 Innovation Drive San Jose, CA 95134 408 544-7000 http://www.altera.com S5V1-1.2 Copyright 2003 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and	Original	EP1S80B956C6 EP1S80B956C7 EP1S80 EP1S80F1020C5 EP1S80F1508C6 EP1S80F1508C7 EP1S80* "Stratix IV" Package layout information EP1S25F780C7 EP1S30F780C7 S-51005	PDF
2929 transistor Abstract: sun 2309 Text: Section I. Stratix Device Family Data Sheet This section provides designers with the data sheet specifications for Stratix devices. They contain feature definitions of the internal architecture, configuration and JTAG boundary-scan testing information, DC operating conditions, AC timing parameters, a reference to power	Original	2003kage 2929 transistor sun 2309	PDF
EP1S60 Abstract: No abstract text available Text: Section I. Stratix Device Family Data Sheet This section provides designers with the data sheet specifications for Stratix devices. They contain feature definitions of the internal architecture, configuration and JTAG boundary-scan testing information, DC operating conditions, AC timing parameters, a reference to power	Original		PDF
EP1S25F780C7 Abstract: EP1S30F780C7 Text: Section I. Stratix Device Family Data Sheet This section provides designers with the data sheet specifications for Stratix devices. They contain feature definitions of the internal architecture, configuration and JTAG boundary-scan testing information, DC operating conditions, AC timing parameters, a reference to power	Original	EP1S80B956C6 EP1S80B956C7 EP1S80 EP1S80F1020C5 EP1S80F1508C6 EP1S80F1508C7 EP1S80* EP1S25F780C7 EP1S30F780C7	PDF
diode jd 4.7-16 Abstract: MA4001 Text: Stratix Device Handbook, Volume 1 101 Innovation Drive San Jose, CA 95134 408 544-7000 http://www.altera.com S5V1-1.2 Copyright 2003 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and	Original	166-MHz diode jd 4.7-16 MA4001	PDF
876 pin bga Abstract: logic diagram to setup adder and subtractor S51005-2 EP1S60 Text: Stratix Device Handbook, Volume 1 101 Innovation Drive San Jose, CA 95134 408 544-7000 http://www.altera.com S5V1-3.4 Copyright 2006 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and	Original		PDF

Privacy Settings

MRAM PCI Search Results

MRAM PCI Result Highlights (5)

MRAM PCI Datasheets Context Search

HC1S40

HC1S60

circuit diagram of half adder

logic diagram to setup adder and subtractor

4046 PLL Designers Guide

IT 8572E

vhdl code for PLL

circuit diagram of full subtractor circuit

Altera Stratix V

74HC230

EP2S90

spi sata controller

SSTL-18

Stratix 8300

simple block diagram for digital clock

verilog sample code for max1619

EP2S90F1020C5

Untitled

"Stratix IV" Package layout information

2929 transistor

EP1S60

EP1S25F780C7

diode jd 4.7-16

876 pin bga