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    N74LS1 Search Results

    N74LS1 Result Highlights (5)

    Part ECAD Model Manufacturer Description Download Buy
    SN74LS109ADR Texas Instruments Dual J-K Positive-Edge-Triggered Flip-Flops With Clear and Preset 16-SOIC 0 to 70 Visit Texas Instruments
    SN74LS123NE4 Texas Instruments Dual retriggerable monostable multivibrators 16-PDIP 0 to 70 Visit Texas Instruments Buy
    SN74LS125ADRE4 Texas Instruments Quadruple Bus Buffers With 3-State Outputs 14-SOIC 0 to 70 Visit Texas Instruments Buy
    SN74LS132N Texas Instruments Quad 2-input positive-NAND Schmitt triggers 14-PDIP 0 to 70 Visit Texas Instruments Buy
    SN74LS145NE4 Texas Instruments BCD-To-Decimal Decoders/Drivers 16-PDIP 0 to 70 Visit Texas Instruments Buy
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    N74LS1 Price and Stock

    Rochester Electronics LLC SN74LS161AN

    SN74LS161A SYNCHRONOUS 4-BIT BIN
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    DigiKey SN74LS161AN Bulk 64,049 707
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    Rochester Electronics LLC SN74LS122N

    SN74LS122 RETRIGGERABLE MONOSTAB
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    DigiKey SN74LS122N Bulk 43,266 440
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    Rochester Electronics LLC SN74LS125AD

    SN74LS125A QUADRUPLE BUS BUFFERS
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    DigiKey SN74LS125AD Bulk 21,402 690
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    Rochester Electronics LLC SN74LS107AD

    SN74LS107A Dual J-K Flip-Flops W
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    DigiKey SN74LS107AD Bulk 18,672 261
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    Rochester Electronics LLC SN74LS151N

    SN74LS151 8-LINE TO 1-LINE DATA
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    DigiKey SN74LS151N Bulk 13,579 615
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    N74LS1 Datasheets (266)

    Part ECAD Model Manufacturer Description Curated Type PDF
    N74LS107 Unknown TTL Data Book 1980 Scan PDF
    N74LS107A Unknown TTL Data Book 1980 Scan PDF
    N74LS107D Signetics Dual J-K Flip-Flop Scan PDF
    N74LS107D Signetics Dual J-K Flip-Flop Scan PDF
    N74LS107N Signetics Dual J-K Flip-Flop Scan PDF
    N74LS107N Signetics Dual J-K Flip-Flop Scan PDF
    N74LS107N Signetics Integrated Circuits Catalogue 1978/79 Scan PDF
    N74LS109 Unknown TTL Data Book 1980 Scan PDF
    N74LS109A Unknown TTL Data Book 1980 Scan PDF
    N74LS109AD Signetics Flip-Flops Scan PDF
    N74LS109AN Signetics Dual J-K Positive Edge-Triggered Flip-Flop Scan PDF
    N74LS109AN Signetics Flip-Flops Scan PDF
    N74LS109D Signetics Dual J-K Positive Edge-Triggered Flip-Flop Scan PDF
    N74LS109N Signetics Integrated Circuits Catalogue 1978/79 Scan PDF
    N74LS10A Unknown TTL Data Book 1980 Scan PDF
    N74LS10D Signetics Triple Three-Input NAND / AND Gates Scan PDF
    N74LS10D Signetics Triple 3-Input NAND / AND Gates Scan PDF
    N74LS10F Signetics Triple 3-Input NAND Gate Scan PDF
    N74LS10N Signetics Triple Three-Input NAND / AND Gates Scan PDF
    N74LS10N Signetics Triple 3-Input NAND Gate Scan PDF
    ...

    N74LS1 Datasheets Context Search

    Catalog Datasheet MFG & Type PDF Document Tags

    sr flip flop

    Abstract: DN74LS113 MA161
    Text: N74LS113 LS TTL DN74LS Series D N 7 4 L S 1 1 3 ^ 7 ^ U S 3 Dual J-K Negative Edge-Triggered F lip -F lo p s with Set) • Description P-l D N74LS113 contains tw o negative-edge triggered J-K flip­ flop circuits, each w ith independent clock-CP, J, K, and


    OCR Scan     		PDF DN74LS DN74LS113 DN74LS113 14-pin S0-140) MA161. trS15ns, sr flip flop MA161

    Untitled

    Abstract: No abstract text available
    Text: 54/7412 54LS/74LS12 ORDERING CODE PACKAGES PIN C O N F. PIN CONFIGURATION See Section 9 for further Package and Ordering Information. C O M M ERCIAL R A N G ES =5V ±5%; T a =0“C to *70"C VC C Plastic D IP Fig. A N7412N • N74LS12N Ceramic D IP Fig. A


    OCR Scan     		PDF 54LS/74LS12 N7412N N7412F N74LS12F N74LS12N S5412F S5412W S54LS12W 54H/74H 54LS/74LS

    Untitled

    Abstract: No abstract text available
    Text: LS TTL DN74LS Series N74LS109 D N 7 4 L S 1 0 9 Dual J-K Positive Edge-Triggered F lip-F lops with S et and Reset • Description P-2 D N74LS109 contains two positive-edge triggered J-K flipflop circuits, each w ith independent clock-CP, J, K, and direct-coupled set and reset input terminals.


    OCR Scan     		PDF DN74LS DN74LS109 N74LS109 MA161

    ma161

    Abstract: No abstract text available
    Text: LS TTL DN74LS Series N74LS112 N74LS112 Dual J-K Negative Edge-Triggered F lip-F lops with S et and Reset • P-2 Description D N74LS112 contains two negative-edge triggered J-K flip­ flop circuits, each w ith independent clock-CP, J , K, and direct-coupled set and reset in p u t term inals.


    OCR Scan     		PDF DN74LS DN74LS112 16-ptn 16-pin S0-160) ma161

    DN74LS139

    Abstract: SO-16D
    Text: LS TTL DN74LS Series N74LS139 N74LS139 Kj 7 4 . ls Dual 2 - lin e to 4 - lin e D ecoders / D em ultiplexers • Description D N74LS139 contains two 2-bit binary to quaternary de­ coder/dem ultiplexer circuits, each w ith independent enable in put term inals.


    OCR Scan     		PDF DN74LS DN74LS139 DN74LS139 16-pin SO-16D) SO-16D

    Untitled

    Abstract: No abstract text available
    Text: I LS TTL DN74LS Series N74LS153 N74LS153 Dual 4 -lin e to 1 -lin e Data Selectors / Multiplexers • Description P-2 D N74LS153 contains tw o 4-line to 1-line data selector/ m ultiplexer circuits. ■ Features • • • • Independent enable input for each circuit


    OCR Scan     		PDF DN74LS DN74LS153 N74LS153 IC20- IC30-

    74L5

    Abstract: No abstract text available
    Text: 74LS197 Signetics Counter Presettable 4-Bit Binary Ripple Counter Product Specification Logic Products FEATURES TYPE PIN CONFIGURATION 16mA COMMERCIAL RANGE Vcc = 5V ±5%; Ta = 0°C to + 70”C PACKAGES Plastic DIP N74LS197N Plastic SO-14 N74LS197D NOTE: For information regarding devices processed to Military Specifications, see the Signetics Military Products


    OCR Scan     		PDF 74LS197 40MHz N74LS197N N74LS197D 1N916, 1N3064, 500ns 500ns 74L5

    400M

    Abstract: DN74LS155 MA161
    Text: LS TTL DN74LS Series D N 7 4 L S 1 5 5 i\j N74LS155 74- 15 5 Dual 2-line to 4-line Decoders/ Demultiplexers • Description P-2 D N74LS155 contains tw o 2-bit binary decoder/dem ultiplexer circuits. to quarternary ■ Features • • • • Low o u tp u t im pedance


    OCR Scan     		PDF DN74LS DN74LS155 DN74LS155 16-pin SO-16D) 03-line 400M MA161

    DN74LS139

    Abstract: No abstract text available
    Text: LS TTL DN74LS Series N74LS139 N74LS139 Kj 7 4 . ls Dual 2 - lin e to 4 - lin e D ecoders / D em ultiplexers • Description D N74LS139 contains two 2-bit binary to quaternary de­ coder/dem ultiplexer circuits, each w ith independent enable in put term inals.


    OCR Scan     		PDF DN74LS DN74LS139 DN74LS139 16-pin SO-16D)

    DN74LS193

    Abstract: No abstract text available
    Text: ! N74LS193 LS T T L DN74LS Series D N 7 4 L S 1 9 3 Synchronous 4 - b it Binary U p /D o w n Dual Clock Counters with R eset P-2 • Description D N74LS193 is a synchronous hexadecim al (4-bit binary) up /d o w n co u n ter w ith direct-coupled reset in p u t and set


    OCR Scan     		PDF DN74LS DN74LS193 DN74LS193 32MHz 16-pin

    7412 pin configuration

    Abstract: 74LS N7412F N7412N N74LS12F N74LS12N S5412F S5412W S54LS12F S54LS12W
    Text: PIN CONFIGURATION 54/7412 54LS/74LS12 ORDERING CODE PACKAGES See Section 9 for further Package and Ordering Information. PIN C O N F. C O M M ER C IA L RANGES VCC = SV ± 5%; T a = 0“ C to *70"C P lastic DIP Fig. A N7412N • N74LS12N C era m ic DIP Fig. A


    OCR Scan     		PDF 54LS/74LS12 N7412N N74LS12N N7412F N74LS12F S5412F S54LS12F S5412W S54LS12W 54H/74H 7412 pin configuration 74LS N7412F N7412N N74LS12N S5412F S5412W S54LS12F S54LS12W

    9013N

    Abstract: No abstract text available
    Text: I N74LS191 LS TTL DN74LS Series N74LS191 Synchronous 4 -b it Binary U p /D ow n Counters with U p /D ow n Mode Control • Description P -2 D N74LS191 is a synchronous 4-bit binary (hexadecim al) co u ter w ith u p /d o w n control inputs and set input.


    OCR Scan     		PDF DN74LS DN74LS191 N74LS191 16-pin 9013N

    DN74LS151

    Abstract: MA161
    Text: I N74LS151 LS TTL DN74LS Series N74LS151 8 -lin e to 1 -lin e Data • S e le c to r s / Multiplexers P-2 Description D N74LS151 is an 8-line to 1-line data selector/m ultiplexer. ■ Features • • • • Enable in p u t C om plem entary o u tp u ts


    OCR Scan     		PDF DN74LS DN74LS151 DN74LS151 16-pin SO-16D) MA161

    DN74LS138

    Abstract: No abstract text available
    Text: It LS TTL DN74LS Series D N 7 4 L S 1 3 N74LS138 8 3 -lin e to 8 -lin e Decoders/ Demultiplexers • Description P-2 D N74LS138 is a 3-bit decimal to octal decoder/demulti­ plexer with enable inputs. ■ Features • • Three types o f enable inputs Quaternary to hexadecimal decoder/demultiplexer capa­


    OCR Scan     		PDF DN74LS DN74LS138 DN74LS138 16-pin SO-16D)

    74190

    Abstract: 74LS191 pins ttl 74190 counter 74190 signetics 74190 74191 state diagram 74ls191 function table
    Text: 74190, 191, LS191 Signetics Counters '190 Presettable BCD/Decade Up/Down Counter '191 Presettable 4-Bit Binary Up/Down Counter Product Specification Logic Products FEATURES • Synchronous, reversible counting • BCD/decade—'190 4-bit binary—'191 • Synchronous, reversible counting


    OCR Scan     		PDF LS191 74LS191 25MHz 25MHz N74190N, N74191N, N74LS191N N74LS191D 74190 74LS191 pins ttl 74190 counter 74190 signetics 74190 74191 state diagram 74ls191 function table

    TTL 74156

    Abstract: demultiplexer 3 16 ttl 74156 C005970S
    Text: 74156, LS156 Signetics Decoders/Demultiplexers Dual 2-Line To 4-Line Decoder/Demultiplexer Open Collector Product Specification Logic Products FEATURES • Common Address inputs • True or complement data demultiplexing • Dual 1-of-4 or 1-of-8 decoding


    OCR Scan     		PDF LS156 74LS156 1N916, 1N3064, 500ns 500ns TTL 74156 demultiplexer 3 16 ttl 74156 C005970S

    74LS181

    Abstract: No abstract text available
    Text: PIN CONFIGURATION SPEED/PACKAGE AVAILABILITY 54 F,W 74 A A,F,W PACKAGE LOGIC DIAGRAM •E H |V C C 'E e^enq; I odo[T I SWITCHING CHARACTERISTICS VCC = 5V. TA - 25° C TO OUTPUT tPLH 'PHL Low-to-high High-to-low Data £Even 40 45 60 68 tPLH »PHL Low-to-high


    OCR Scan     		PDF 400S2 74LS181

    IC 74173

    Abstract: ttl 74173 74173 ic ap 5331 8T10 74173 74173+truth+table
    Text: Signelics 74173, LS173 Flip-Flops Quad D-Type Flip-Flop With 3-State Outputs Product Specification Logic Products FEATURES • Edge-triggered D-type register • Gated input enable for hold "do nothing" mode • 3-State output buffers • Gated output enable control


    OCR Scan     		PDF LS173 500ns 500ns IC 74173 ttl 74173 74173 ic ap 5331 8T10 74173 74173+truth+table

    74LS169A

    Abstract: 74LS168A 74S168A S168A 74S169
    Text: 74LS168A, 74LS169A, S168A, S169A Signetics 4-Bit Bidirectional Counters 4-Bit Up/Down Synchronous Counter Product Specification Logic Products FEATURES • Synchronous counting and loading • Up/down counting • Modulo 16 binary counter — '169A • BCD decade counter — ' 168A


    OCR Scan     		PDF 74LS168A, 74LS169A, S168A, S169A 74LS169A 74LS168A 74S168A S168A 74S169

    ic 74153 Multiplexer

    Abstract: application of ic 74153 ic 74153 Multiplexer pin diagram pin DIAGRAM OF IC 74153 IC 74153 Multiplexer 74153 74153 multiplexer ic IC 74LS153 pin diagram ic pin configuration 74153 74153 equivalent
    Text: 74153, LS153, S153 Signetics Multiplexers Dual 4-Line To 1-Line Multiplexer Product Specification Logic Products FEATURES • Non-inverting outputs • Separate enable for each section • Common select inputs • See '253 for 3-state version DESCRIPTION The '153 is a dual 4-input multiplexer


    OCR Scan     		PDF LS153, 74LS153 74S153 1N916, 1N3064, 500ns 500ns ic 74153 Multiplexer application of ic 74153 ic 74153 Multiplexer pin diagram pin DIAGRAM OF IC 74153 IC 74153 Multiplexer 74153 74153 multiplexer ic IC 74LS153 pin diagram ic pin configuration 74153 74153 equivalent

    1 to 16 74154 demultiplexer

    Abstract: 74LS154 decoder TTL 74154 circuit diagram of 74ls154 74ls154 pin configuration of 74LS154 decoder 74LS154 74154 demultiplexer max3633 pin diagram of 74ls154
    Text: Signetics 74154, LSI54 Decoder/Demultiplexers 1-of-16 Decoder/Demultiplexer Product Specification Logic Products FEATURES • 16-line demultiplexing capability • Mutually exclusive outputs • 2-input enable gate for strobing or expansion TYPICAL SUPPLY CURRENT


    OCR Scan     		PDF LSI54 1-of-16 16-line 74LS154 1N916, 1N3064, 500ns 500ns 1 to 16 74154 demultiplexer 74LS154 decoder TTL 74154 circuit diagram of 74ls154 74ls154 pin configuration of 74LS154 decoder 74LS154 74154 demultiplexer max3633 pin diagram of 74ls154

    74194 function table

    Abstract: 74194 universal shift register TTL 74194 74194 design and application shift register 74194 circuit 74194 74194 shift register 74194 shift register waveform 74194 logic diagram N74S194N
    Text: 74194, LS194A, S194 Signetics Shift Registers 4-Bit Bidirectional Universal Shift Register Product Specification Logic Products • Buffered clock and control Inputs • Shift left and shift right capability • Synchronous parallel and serial data transfers


    OCR Scan     		PDF LS194A, 54LS/74LS, 54S/74S, 1N916, 1N3064, 500ns 74194 function table 74194 universal shift register TTL 74194 74194 design and application shift register 74194 circuit 74194 74194 shift register 74194 shift register waveform 74194 logic diagram N74S194N

    74LS113

    Abstract: C0056
    Text: 74LS113, S113 Signetics Flip-Flops Dual J-K Edge-Triggered Flip-Flop Product Specification Logic Products DESCRIPTION T h e '1 1 3 is a dual J-K negative edgetriggered flip-flop featuring individual J, K, S e t and Clock inputs. Th e asynchro­ nous S e t Sq input, w hen LOW , forces


    OCR Scan     		PDF 74LS113, 1N916, 1N3064, 500ns 500ns 74LS113 C0056

    ic 74132

    Abstract: f 74132 LS132 74132 853051 R/ls 74132
    Text: 74132, LS132 SigneHcs Schmitt Triggers Quad 2-Input NAND Schmitt Trigger Product Specification Logic Products The '132 contains four 2-input NAND gates which accept standard TTL input signals and provide standard TTL output levels. They are capable of transforming


    OCR Scan     		PDF LS132 ic 74132 f 74132 LS132 74132 853051 R/ls 74132