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    NAND GATES IN 2 UNITS Search Results

    NAND GATES IN 2 UNITS Result Highlights (5)

    Part ECAD Model Manufacturer Description Download Buy
    TMPM4GQF15FG Toshiba Electronic Devices & Storage Corporation Arm Cortex-M4 processor with FPU Core Based Microcontroller/32bit/P-LQFP144-2020-0.50-002 Visit Toshiba Electronic Devices & Storage Corporation
    TMPM4GRF20FG Toshiba Electronic Devices & Storage Corporation Arm Cortex-M4 processor with FPU Core Based Microcontroller/32bit/P-LQFP176-2020-0.40-002 Visit Toshiba Electronic Devices & Storage Corporation
    TMPM4KMFWAFG Toshiba Electronic Devices & Storage Corporation Arm Cortex-M4 processor with FPU Core Based Microcontroller/32bit/P-LQFP80-1212-0.50-003 Visit Toshiba Electronic Devices & Storage Corporation
    TMPM4MMFWAFG Toshiba Electronic Devices & Storage Corporation Arm Cortex-M4 processor with FPU Core Based Microcontroller/32bit/P-LQFP80-1212-0.50-003 Visit Toshiba Electronic Devices & Storage Corporation
    TMPM4NQF10FG Toshiba Electronic Devices & Storage Corporation Arm Cortex-M4 processor with FPU Core Based Microcontroller/32bit/P-LQFP144-2020-0.50-002 Visit Toshiba Electronic Devices & Storage Corporation

    NAND GATES IN 2 UNITS Datasheets Context Search

    Catalog Datasheet MFG & Type PDF Document Tags

    DM54L00J

    Abstract: No abstract text available
    Text: DM54L00 DM54L00 Quad 2-Input NAND Gates Literature Number: SNOS264A DM54L00 Quad 2-Input NAND Gates General Description This device contains four independent gates each of which performs the logic NAND function Connection Diagram Function Table Dual-In-Line Package


    Original     		PDF DM54L00 DM54L00 SNOS264A DM54L00J DM54L00W C1995 RRD-B30M105

    ACT132

    Abstract: No abstract text available
    Text: MC74AC132, MC74ACT132 Quad 2-Input NAND Schmitt Trigger The MC74AC/74ACT132 contains four 2−input NAND gates which are capable of transforming slowly changing input signals into sharply defined, jitter−free output signals. In addition, they have greater noise margin than conventional NAND gates.


    Original     		PDF MC74AC132, MC74ACT132 MC74AC/74ACT132 PDIP-14 74ACT MC74ACT132 MC74AC132N SO-14 ACT132

    act132

    Abstract: AC-132 MC74AC132 MC74AC132D MC74AC132DR2 MC74AC132N MC74ACT132 MC74ACT132D MC74ACT132DR2 MC74ACT132N
    Text: MC74AC132, MC74ACT132 Quad 2−Input NAND Schmitt Trigger The MC74AC/74ACT132 contains four 2−input NAND gates which are capable of transforming slowly changing input signals into sharply defined, jitter−free output signals. In addition, they have greater noise margin than conventional NAND gates.


    Original     		PDF MC74AC132, MC74ACT132 MC74AC/74ACT132 MC74AC132/D act132 AC-132 MC74AC132 MC74AC132D MC74AC132DR2 MC74AC132N MC74ACT132 MC74ACT132D MC74ACT132DR2 MC74ACT132N

    74ac132

    Abstract: AC132G ACT132G 74AC ACT132 MC74AC132 MC74AC132N MC74ACT132 SOEIAJ-14 MC74AC132NG
    Text: MC74AC132, MC74ACT132 Quad 2−Input NAND Schmitt Trigger The MC74AC/74ACT132 contains four 2−input NAND gates which are capable of transforming slowly changing input signals into sharply defined, jitter−free output signals. In addition, they have greater noise margin than conventional NAND gates.


    Original     		PDF MC74AC132, MC74ACT132 MC74AC/74ACT132 MC74AC132/D 74ac132 AC132G ACT132G 74AC ACT132 MC74AC132 MC74AC132N MC74ACT132 SOEIAJ-14 MC74AC132NG

    AC132G

    Abstract: ACT132G 74ac132 74act132 AC-132G act132 on 74AC ACT132 MC74AC132 MC74AC132N
    Text: MC74AC132, MC74ACT132 Quad 2−Input NAND Schmitt Trigger The MC74AC/74ACT132 contains four 2−input NAND gates which are capable of transforming slowly changing input signals into sharply defined, jitter−free output signals. In addition, they have greater noise margin than conventional NAND gates.


    Original     		PDF MC74AC132, MC74ACT132 MC74AC/74ACT132 AC132G ACT132G 74ac132 74act132 AC-132G act132 on 74AC ACT132 MC74AC132 MC74AC132N

    AC132G

    Abstract: No abstract text available
    Text: MC74AC132, MC74ACT132 Quad 2−Input NAND Schmitt Trigger The MC74AC/74ACT132 contains four 2−input NAND gates which are capable of transforming slowly changing input signals into sharply defined, jitter−free output signals. In addition, they have greater noise margin than conventional NAND gates.


    Original     		PDF MC74AC132, MC74ACT132 MC74AC/74ACT132 MC74AC132/D AC132G

    74ac132

    Abstract: 74ACT132 ACT132 MC74AC132 MC74AC132D MC74AC132DR2 MC74AC132N MC74ACT132 MC74ACT132D MC74ACT132DR2
    Text: MC74AC132, MC74ACT132 Quad 2-Input NAND Schmitt Trigger The MC74AC/74ACT132 contains four 2–input NAND gates which are capable of transforming slowly changing input signals into sharply defined, jitter–free output signals. In addition, they have greater noise margin than conventional NAND gates.


    Original     		PDF MC74AC132, MC74ACT132 MC74AC/74ACT132 r14525 MC74AC132/D 74ac132 74ACT132 ACT132 MC74AC132 MC74AC132D MC74AC132DR2 MC74AC132N MC74ACT132 MC74ACT132D MC74ACT132DR2

    AC132

    Abstract: 74ac132
    Text: MC74AC132, MC74ACT132 Quad 2-Input NAND Schmitt Trigger The MC74AC/74ACT132 contains four 2–input NAND gates which are capable of transforming slowly changing input signals into sharply defined, jitter–free output signals. In addition, they have greater noise margin than conventional NAND gates.


    Original     		PDF MC74AC132, MC74ACT132 MC74AC/74ACT132 74ACT MC74ACT132 MC74AC132N AC132 74AC13 MC74ACT132N 74ac132

    DM74S00N

    Abstract: DM54S00 DM54S00J DM54S00W DM74S00 DM74S00M J14A M14A N14A W14B
    Text: DM54S00 DM74S00 Quad 2-Input NAND Gates General Description This device contains four independent gates each of which performs the logic NAND function Connection Diagram Dual-In-Line Package TL F 6489 – 1 Order Number DM54S00J DM54S00W DM74S00M or DM74S00N


    Original     		PDF DM54S00 DM74S00 DM54S00J DM54S00W DM74S00M DM74S00N C1995 RRD-B30M105 DM74S00N J14A M14A N14A W14B

    DM74S00N

    Abstract: DM74S00 DM54S00J DM54S00W DM74S00M J14A M14A N14A W14B
    Text: DM74S00 Quad 2-Input NAND Gates General Description This device contains four independent gates each of which performs the logic NAND function. Connection Diagram Dual-In-Line Package DS006489-1 Order Number DM54S00J, DM54S00W, DM74S00M or DM74S00N See Package Number J14A, M14A, N14A or W14B


    Original     		PDF DM74S00 DS006489-1 DM54S00J, DM54S00W, DM74S00M DM74S00N DS006489 DM74S00 DM54S DM74S DM74S00N DM54S00J DM54S00W J14A M14A N14A W14B

    f6654

    Abstract: DM54L00J C1995 DM54L00 DM54L00W J14A W14B f 6654
    Text: DM54L00 Quad 2-Input NAND Gates General Description This device contains four independent gates each of which performs the logic NAND function Connection Diagram Function Table Dual-In-Line Package Y e AB Inputs Output A B Y L L H H L H L H H H H L H e High Logic Level


    Original     		PDF DM54L00 DM54L00J DM54L00W C1995 RRD-B30M105 DM54L00 f6654 DM54L00W J14A W14B f 6654

    Untitled

    Abstract: No abstract text available
    Text: GD54/74HC00, GD54/74HCT00 QUAD 2-INPUT NAND GATES General Description These devices are identical in pinout to the 54/74LS00. They contain four independent 2-input NAND gates. These devices are characterized for operation over wide temperature ranges to meet in­


    OCR Scan     		PDF GD54/74HC00, GD54/74HCT00 54/74LS00.

    TTL 74HC00

    Abstract: 74LS00 TTL TTL 74ls00 74LS00 gate diagram 74ls00 74LS00 function table pin configuration logic symbol 74LS00 logic symbol 74LS00 74HC00 5V 74HC00
    Text: GD54/74HC00, GD54/74HCT00 QUAD 2-INPUT NAND GATES General Description These devices are identical in pinout to the 54/74LS00. They contain four independent 2-input NAND gates. These devices are characterized for operation over wide temperature ranges to meet in­


    OCR Scan     		PDF GD54/74HC00, GD54/74HCT00 54/74LS00. GD74HCT00 GD54HCT00 D0Q457Q TTL 74HC00 74LS00 TTL TTL 74ls00 74LS00 gate diagram 74ls00 74LS00 function table pin configuration logic symbol 74LS00 logic symbol 74LS00 74HC00 5V 74HC00

    74LS00 pinout

    Abstract: GD74HC00 pin configuration logic symbol 74LS00 logic symbol 74LS00 74HC00 5V 74HC00 74hc00 and gates TTL 74HC00 74HC GD54HC00
    Text: GDS4/74HC00, GD54/74HCT00 QUAD 2-INPUT NAND GATES General Description These devices are identical in pinout to the 54/74LS 00. They contain four independent 2-input NAND gates. These devices are characterized for operation over wide temperature ranges to meet in­


    OCR Scan     		PDF GD54/74HC00, GD54/74HCT00 54/74LS00. GD74HCT00 GD54HCT00 74LS00 pinout GD74HC00 pin configuration logic symbol 74LS00 logic symbol 74LS00 74HC00 5V 74HC00 74hc00 and gates TTL 74HC00 74HC GD54HC00

    Untitled

    Abstract: No abstract text available
    Text: o National ÆSt Semiconductor DM54L00 Quad 2-lnput NAND Gates General Description This device contains four independent gates each of which performs the logic NAND function. Connection Diagram Function Table Dual-In-Line Package Y = AB Output Inputs H “


    OCR Scan     		PDF DM57L

    Untitled

    Abstract: No abstract text available
    Text: GD54/74HC132, GD54/74HCT132 QUAD 2-INPUT SCHMITT-TRIGGER NAND GATES General Description These devices are identical in pinout to the 5 4 /7 4 L S 1 3 2 . They contain four independent 2-Input NAND gates. Each input has hysteresis and can, therefore, be used to enhance noise immunity


    OCR Scan     		PDF GD54/74HC132, GD54/74HCT132

    DM54L00J

    Abstract: No abstract text available
    Text: June 1989 Semiconductor DM54L00 Quad 2-Input NAND Gates General Description This device contains four independent gates each of which performs the logic NAND function. Connection Diagram Function Table Dual-In-Line Package Y = AB Inputs Output A B Y L L H


    OCR Scan     		PDF DM54L00 DM54L00J DM54L00W 105/Printed

    DM54S20J

    Abstract: DM54S20W DM74S20N J14A N14A W14B DM74S20
    Text: , March 1989 DM54S20/DM74S20 Dual 4-Input NAND Gates General Description This device contains two independent gates each of which performs the logic NAND function. Connection Diagram Dual-In-Line Package 02 M çc C2 13 NC 12 I - B2 111 A2 10 9 — 2 1 Al 13


    OCR Scan     		PDF DM54S20/DM74S20 TL/F/6449-1 DM54S20J, DM54S20W DM74S20N TL/F/6449 RRD-B30M105/Printed DM54S20J J14A N14A W14B DM74S20

    GD74HC20

    Abstract: GD74HCT20
    Text: GD54/74HC20, GD54/74HCT20 DUAL 4-INPUT NAND GATES General Description These devices Pin Configuration are identical in pinout to the 5 4 /7 4 L S 2 0 . They contain two independent 4 -input NAND gates. These devices are characteriz­ ed for operation over wide temperature ranges to


    OCR Scan     		PDF GD54/74HC20, GD54/74HCT20 20/uA GD74HCT20 GD54HCT20 GD74HC20 GD74HCT20

    Untitled

    Abstract: No abstract text available
    Text: June 1989 DM54S00/DM74S00 Quad 2-Input NAND Gates General Description This device contains four independent gates each of which performs the logic NAND function. Connection Diagram Dual-In-Line Package V cc B4 A4 Y4 B3 A3 Y3 AI Bl Y1 A2 B2 Y2 GMD TL/F/6489-1


    OCR Scan     		PDF DM54S00/DM74S00 TL/F/6489-1 DM54S00J, DM54S00W, DM74S00M DM74S00N 105/Printed

    DM54L10

    Abstract: DM54L10J DM54L10W J14A W14B
    Text: , June 1989 DM54L10 Triple 3-Input NAND Gates General Description This device contains three independent gates each of which performs the logic NAND function. Connection Diagram Dual-In-Line Package Vcc Cl |,4 Y1 13 C3 B3 11 12 A3 10 Y3 9 8 =5 ED 1 A1 2 D -


    OCR Scan     		PDF DM54L10 DM54L10J DM54L10W TL/F/6619-1 TL/F/6619 RRD-B30M105/Printed DM54L10 J14A W14B

    GD74HCT03

    Abstract: GD74HC03
    Text: GD54/74HC03, GD54/74HCT03 QUAD 2-INPUT NAND GATES WITH OPEN-DRAIN OUTPUTS General Description Pin Configuration These devices are identical in pinout to the 54/74LS03. They contain four independent 2-Input NAND gates. The open-drain outputs require pullup resistors to perform correctly. With suitable pullup resistors, these devices can be used in activelow wired-OR or active-high wired-AND applica­


    OCR Scan     		PDF GD54/74HC03, GD54/74HCT03 54/74LS03. GD74HCT03 GD53HCT03 GD74HCT03 GD74HC03

    Untitled

    Abstract: No abstract text available
    Text: R C H II- D S E M IC O N D U C T O R tm MM74HC00 Quad 2-Input NAND Gate General Description Features These NAND gates utilize advanced silicon-gate CMOS technology to achieve operating speeds similar to LS-TTL gates with the low power consumption of standard CMOS in­


    OCR Scan     		PDF MM74HC00 54HC/74HC 54LS/74LS 250i0 MM74HC00N

    DM7413N

    Abstract: No abstract text available
    Text: co 5 p^. K&M National s Q co 5 in 2 o Sim Semiconductor DM5413/DM7413 Dual 4-Input NAND Gates with Schmitt Trigger Inputs General Description Absolute Maximum Ratings Note d This device con tains tw o independent gates each of w hich perform s the logic NAND fun ction. Each input


    OCR Scan     		PDF DM5413/DM7413 F/6502-1 tti-55 400S1 DM7413N