Untitled
Abstract: No abstract text available
Text: LTC2123 Dual 14-Bit 250Msps ADC with JESD204B Serial Outputs Features n n n n n n n n n n n n Description 5Gbps JESD204B Interface 70dBFS SNR 90dBFS SFDR Low Power: 864mW Total Single 1.8V Supply Easy to Drive 1.5VP-P Input Range 1.25GHz Full Power Bandwidth S/H
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LTC2123
14-Bit
250Msps
JESD204B
70dBFS
90dBFS
864mW
25GHz
48-Lead
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Untitled
Abstract: No abstract text available
Text: LTC2123 Dual 14-Bit 250Msps ADC with JESD204B Serial Outputs Features n n n n n n n n n n n n Description 5Gbps JESD204B Interface 70dBFS SNR 90dBFS SFDR Low Power: 864mW Total Single 1.8V Supply Easy to Drive 1.5VP-P Input Range 1.25GHz Full Power Bandwidth S/H
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LTC2123
14-Bit
250Msps
JESD204B
70dBFS
90dBFS
864mW
25GHz
48-Lead
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Untitled
Abstract: No abstract text available
Text: LTC2122 Dual14-Bit 170Msps ADC with JESD204B Serial Outputs Features Description 6.0Gbps JESD204B Interface n Only One Output Lane Required for Both ADCs FS < = 150Msps n 70dBFS SNR n 90dBFS SFDR n Low Power: 751mW Total n Single 1.8V Supply n Easy to Drive 1.5V
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LTC2122
Dual14-Bit
170Msps
JESD204B
150Msps)
70dBFS
90dBFS
751mW
25GHz
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circuit diagram of half adder
Abstract: 2-bit half adder 9 TAP LUT adaptive filter noise cancellation SPEED CON 5200 datasheet for full adder and half adder XC4000 XC4000E XC4000EX xilinx FPGA IIR Filter
Text: APPLICATION NOTE XAPP 055 January 9, 1997 Version 1.1 Block Adaptive Filter Application Note by Bill Allaire and Bud Fischer Summary This application note describes a specific design for implementing a high speed, full precision, adaptive filter in the
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XC4000E/EX
XC4000
circuit diagram of half adder
2-bit half adder
9 TAP LUT
adaptive filter noise cancellation
SPEED CON 5200
datasheet for full adder and half adder
XC4000E
XC4000EX
xilinx FPGA IIR Filter
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xilinx FPGA IIR Filter
Abstract: XC4000E XC4000EX
Text: APPLICATION NOTE XAPP 055 August 15, 1996 Version 1.0 Block Adaptive Filter Application Note by Bill Allaire and Bud Fischer Summary This application note describes a specific design for implementing a high speed, full precision, adaptive filter in the
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XC4000E/EX
xilinx FPGA IIR Filter
XC4000E
XC4000EX
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MK5025
Abstract: No abstract text available
Text: APPLICATION NOTE MK5025 TRANSPARENT MODE INTRODUCTION The SGS-Thomson X.25 Link Level Controller MK5025 is a VLSI device which provides a complete link level data communication control conforming to the 1984 CCITT version of X.25. The MK5025 also supports X.32 (XID) and X.75 as
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MK5025
MK5025)
MK5025
MK5025,
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MK5025
Abstract: No abstract text available
Text: APPLICATION NOTE MK5025 TRANSPARENT MODE INTRODUCTION The SGS-Thomson X.25 Link Level Controller MK5025 is a VLSI device which provides a complete link level data communication control conforming to the 1984 CCITT version of X.25. The MK5025 also supports X.32 (XID) and X.75 as
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MK5025
MK5025)
MK5025
MK5025,
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PXB 4325
Abstract: PXB 4310 W25 smd siemens k25 PXB4325E
Text: ICs for Communications ATM Switching Preprocessor ASP PXB 4325 E Version 1.1 Preliminary Data Sheet 08.98 DS 1 PXB 4325 E Revision History: Current Version: 08.98 Previous Version: None Page Page in previous (in current Version Version) Subjects (major changes since last revision)
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h221
Abstract: 3TF32 sth-22 TSA47
Text: STH221 MULDEX IC FOR MULTIMEDIA TELESERVICES HCMOS SEA OF GATE TECHNOLOGY 64 PINS QUAD FLAT PACKAGE TWO MODES OF OPERATION: STANDALONE, MICROPROCESSOR INTERFACE FOR 8/16/32 BIT MICROPROCESSORS TRANSMITTER FUNCTIONS: Implementation of two electrical interfaces:
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STH221
64kbit/s
64kbit/srwise
h221
3TF32
sth-22
TSA47
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N8222
Abstract: 28-22-21 bt8222
Text: Bt8222 ATM Transmitter/Receiver with UTOPIA Interface The Bt8222 ATM Transmitter/Receiver with UTOPIA Level 1 interface provides a single-access ATM service termination for User-to-Network UNI and Network-to-Network Interfacing (NNI) in conformance with ATM Forum UNI and NNI
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Bt8222
Bt8222
TR-TSV-000772,
TR-TSV-000773,
TR-NWT-000253,
T1S1/92-185;
N8222
28-22-21
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n8223
Abstract: N-822 CN8223EPF AD6116 78P7200 CN8223 BT8222EPFE PROCESS CONTROL TIMER using 555 ic
Text: CN8223 ATM Transmitter/Receiver with UTOPIA Interface The CN8223 ATM Transmitter/Receiver with UTOPIA Level 1 interface provides a single-access ATM service termination for User-to-Network UNI and Network-to-Network Interfacing (NNI) in conformance with ATM Forum UNI and NNI
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CN8223
CN8223
TR-TSV-000772,
TR-TSV-000773,
TR-NWT-000253,
T1S1/92-185;
n8223
N-822
CN8223EPF
AD6116
78P7200
BT8222EPFE
PROCESS CONTROL TIMER using 555 ic
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H221
Abstract: TSN2 muldex PQFP64 STH221 EN-EL1
Text: STH221 MULDEX IC FOR MULTIMEDIA TELESERVICES HCMOS SEA OF GATE TECHNOLOGY 64 PINS QUAD FLAT PACKAGE TWO MODES OF OPERATION: STANDALONE, MICROPROCESSOR INTERFACE FOR 8/16/32 BIT MICROPROCESSORS TRANSMITTER FUNCTIONS: Implementation of two electrical interfaces:
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STH221
64kbit/s
H221
TSN2
muldex
PQFP64
STH221
EN-EL1
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MA28140
Abstract: audi Security Transponder DS3839-7 decod and counter and seven segment timer PSS-04-107 sliding
Text: MA28140 MA28140 Packet Telecommand Decoder • Built-in Command Pulse Distribution Unit Core Logic ■ Radiation Hard to 1MRads Si ■ High SEU Immunity, Latch-up Free 12 14 TCC0-5 TCS0-5 TCA0-5 VDD GND PTD CPDUSTN CPDUEN CPDUDIV MAPSTN MAPCK MAPDSR MAPDTR
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MA28140
MA28140
audi Security Transponder
DS3839-7
decod and counter and seven segment timer
PSS-04-107
sliding
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stk 3120
Abstract: 80c186 obsolete date CR056 DT 8210 IC TSC 232 CPE cr038 DT 8210 stk 432 070 BT8210EPF 8210 microprocessor
Text: Advance Information This document contains information on a product under development. The parametric information contains target parameters that are subject to change. Printed exclusively for DataRace Bt8209/8210 SMDS Control and Reassembly Formatter SCARF
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Bt8209/8210
Bt8209
Bt8210
stk 3120
80c186 obsolete date
CR056
DT 8210 IC
TSC 232 CPE
cr038
DT 8210
stk 432 070
BT8210EPF
8210 microprocessor
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bip 109
Abstract: 78P7200 CN8223 CN8223EPF
Text: CN8223 ATM Transmitter/Receiver with UTOPIA Interface The CN8223 ATM Transmitter/Receiver with UTOPIA Level 1 interface provides a single-access ATM service termination for User-to-Network UNI and Network-to-Network Interfacing (NNI) in conformance with ATM Forum UNI and NNI
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CN8223
CN8223
TR-TSV-000772,
TR-TSV-000773,
TR-NWT-000253,
T1S1/92-185;
bip 109
78P7200
CN8223EPF
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BT8222KPF
Abstract: atm header error checking 78P7200 CN8223 CN8223EPF e3 frame formatter
Text: CN8223 ATM Transmitter/Receiver with UTOPIA Interface The CN8223 ATM Transmitter/Receiver with UTOPIA Level 1 interface provides a single-access ATM service termination for User-to-Network UNI and Network-to-Network Interfacing (NNI) in conformance with ATM Forum UNI and NNI
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CN8223
CN8223
TR-TSV-000772,
TR-TSV-000773,
TR-NWT-000253,
T1S1/92-185;
BT8222KPF
atm header error checking
78P7200
CN8223EPF
e3 frame formatter
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Untitled
Abstract: No abstract text available
Text: DALLAS SEM ICONDUCTOR DS3131 Preliminary Data Sheet V1 August 6, 1998 DALLAS SEMICONDUCTOR DS3131 BOSS Bit and Octet Synchronous HDLC CONTROLLER 40 Port / 40 Channel HDLC Controller with Options for Local Bus Access & an Octet Synchronous Port Preliminary Data Sheet
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DS3131
DS3131
DS3131.
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GG1Q
Abstract: No abstract text available
Text: 1.0 Product Description 1.1 Introduction Figure 1-1 is a detailed block diagram o f the Bt8222. For transmission from the host system, octet-wide data is input from the UTOPIA or FIFO ports. The host data is assembled into ATM cells and then formatted for serial line transmission
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Bt8222.
GG1Q
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L8222
Abstract: OQ 051
Text: 1.0 Product Description 1.1 Introduction Figure 1-1 is a detailed block diagram of the Bt8222. For transmission from the host system, octet-wide data is input from the UTOPIA or FIFO ports. The host data is assembled into ATM cells and then formatted for serial line transmission
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Bt8222.
L822201
L8222
OQ 051
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SX1601
Abstract: Simulex ba522
Text: r ’«no Sinralex Corporation Product Specification SX1601 IPI-2 DISK DRIVE INTERFACE PROTOCOL CIRCUIT Features • Generates and Checks IPI Bus parity Directs Data Bus Controls to the SERDES / FORMATTER CIRCUIT • Internal FIFO buffers disk write data Directs Command / Response Bus Controls to
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SX1601
SX16Q1
Simulex
ba522
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system functions and objectives for 4-bit synchronization counter
Abstract: PM4341 PM7321 T1X14
Text: -an/ir1pM c's,era'inc- r I Y IV * PRELIMINARY INFORMATION PM7321PLPP PHYSICAL LAYER PROTOCOL PROCESSOR FEATURES • Implements the ATM physical layer for Broadband ISDN according to CCITT Recommendation 1.432. • Implements the Physical Layer Convergence Protocol for DS1 and DS3 based
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PM7321PLPP
TA-TSY-000773
TA-TSY-000772
910812S4
system functions and objectives for 4-bit synchronization counter
PM4341
PM7321
T1X14
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receiver 4310 fea
Abstract: siemens ecu scheme
Text: SIEMENS ICs for Communications ATM Switching Preprocessor ASP PXB 4325 E Version 1.1 Preliminary Data Sheet 08.98 DS 1 PXB 4325 E Revision History: Current Version: 08.98 Previous Version: None Page in previous Version Page (in current Version) Subjects (major changes since last revision)
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Untitled
Abstract: No abstract text available
Text: / = T SGS-THOMSON ^ 7 # * 0^0 [H3 [E[L[l©Tri^ Q R0D©S APPLICATION NOTE MK5025 TRANSPARENT MODE INTRODUCTION CONTROL AND STATUS REGISTER OPERATION The SG S-Thom son X.25 Link Level Controller (MK5025) is a VLSI device which provides a com plete link level data com m unication control con
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MK5025
MK5025)
MK502e
K5025
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PS 9829 m
Abstract: Q559 int 6400 PS 9829 B
Text: GO UL D S E M I C O N D U C T O R 4055916 GÖULD SEMICONDUCTOR D I V % pe. |. n »IV QBE D | MDSS^lt, D G l G a a D 0 J ~ 03E 10220 D Intelligent Slave Physical Interface Controller IPI-3 Electronics 7 ^ 5 5 '3 3 - /S' P r e lim in a r y D a ta S h e e t
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S61393
16-bit
G0030
PS 9829 m
Q559
int 6400
PS 9829 B
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