PC111
Abstract: No abstract text available
Text: Revision 1.5 ColdFire Processor Family A Version 4 ColdFire Reference Design ColdFire Instruction Set Enhancements This appendix details the new opcodes implemented as part of the Revision B ISA_B enhancements to the basic ColdFire instruction set architecture. In some cases, the
|
Original
|
PDF
|
|
8 BIT ALU
Abstract: 4 bit right left shift register ics 8 bit full adder 32-bit adder 8 bit adder 8 bit carry select adder
Text: B Compute Operations B.2.3 Shifter Operations Shifter operations are described in this section. Table B.6 summarizes the syntax and opcodes for the shifter operations. The succeeding pages provide detailed descriptions of each operation. The shifter operates on the register file’s 32-bit fixed-point fields bits 398 . Two-input shifter operations can take their y-input from the register
|
Original
|
PDF
|
32-bit
R11-R8
F11-F8)
R15-R12
F15-F12)
8 BIT ALU
4 bit right left shift register ics
8 bit full adder
32-bit adder
8 bit adder
8 bit carry select adder
|
SERVICE MANUAL tv hyundai
Abstract: SERVICE MANUAL tv TCL LABTOOL-48 cmos 4004 Intel 4001 64LQFP GMS81508 GMS81508A GMS81516 GMS81516A
Text: GMS81508A GMS81516A USER’S MANUAL Revision History Rev 2.2 Dec. 1998 Add the package dimension for 64LQFP on page 3-1, 4-1. Rev 2.1 (Nov. 1998) Operating Temperature, -10~75°C is extended to -20~85°C. Add the unused port guidance on page 55. Correct errata for opcode of “EOR [dp+X], EOR [dp]+Y, EOR {X}” in “Instruction Set”.
|
Original
|
PDF
|
GMS81508A
GMS81516A
64LQFP
GMS81516AT
SERVICE MANUAL tv hyundai
SERVICE MANUAL tv TCL
LABTOOL-48
cmos 4004
Intel 4001
GMS81508
GMS81508A
GMS81516
GMS81516A
|
MC9S12DP256
Abstract: sae j1850 pwm controller 68HC11 68HC12 HCS12 J1850 MC9S12DJ256
Text: A FLASH MCU SOLUTION MC9S12DJ256 16-bit Microcontroller FEATURES BENEFITS HIGH-PERFORMANCE 16-BIT HCS12 CPU CORE • 25 MHz bus operation at 5V for 40 nsec minimum instruction cycle time TARGET APPLICATIONS • Opcode compatible with the 68HC11 and 68HC12
|
Original
|
PDF
|
MC9S12DJ256
16-bit
HCS12
68HC11
68HC12
68HC12ompiler
MC9S12DP256
sae j1850 pwm controller
68HC12
J1850
MC9S12DJ256
|
68hc11 Controller Area Network
Abstract: 68HC11 68HC12 DG128 HCS12 MC9S12DG128 Motorola HCS12 Reference Manual
Text: A FLASH MCU SOLUTION MC9S12DG128 16-bit Microcontroller FEATURES BENEFITS HIGH-PERFORMANCE 16-BIT HCS12 CPU CORE • 25 MHz bus operation at 5V for 40 nsec minimum instruction cycle time TARGET APPLICATIONS • Opcode compatible with the 68HC11 and 68HC12
|
Original
|
PDF
|
MC9S12DG128
16-bit
HCS12
68HC11
68HC12
68HC12
EB386/D
68hc11 Controller Area Network
DG128
MC9S12DG128
Motorola HCS12 Reference Manual
|
radix-2 dit fft flow chart
Abstract: DSP56300 mac 226 40N160 40n220
Text: Appendix C BENCHMARK PROGRAMS C-1 INTRODUCTION The following benchmarks illustrate the source code syntax and programming techniques for the DSP56300 Core. The assembly language source is organized into 6 columns as shown below. Label Opcode Operands X Bus Data Y Bus Data Comment
|
Original
|
PDF
|
DSP56300
50MHz
60MHz
radix-2 dit fft flow chart
mac 226
40N160
40n220
|
Untitled
Abstract: No abstract text available
Text: Features • • • • • • • • • • • • • • Compatible with an Embedded 32-bit Microcontroller Part of the Memory Controller Interface of the Flash Block with the 32-bit Internal Bus Increases Performance in ARM Thumb® Mode for Opcode Fetch
|
Original
|
PDF
|
32-bit
32-bit
6084AS
|
opcode table for 8086
Abstract: 8086 opcode table 8086 opcode 8086 opcode sheet 8086 opcode sheet free download 8086 mnemonic code 8086 mnemonic opcode intel 8086 opcode sheet imm32 intel 8086
Text: X 60 X 60.1 XADD—Exchange and Add Opcode Instruction Description 0F C0/r XADD r/m8,r8 Exchange r8 and r/m8; load sum into r/m8. 0F C1/r XADD r/m16,r16 Exchange r16 and r/m16; load sum into r/m16. 0F C1/r XADD r/m32,r32 Exchange r32 and r/m32; load sum into r/m32.
|
Original
|
PDF
|
r/m16
r/m16;
r/m16.
r/m32
r/m32;
r/m32.
Intel486
Virtual-8086
opcode table for 8086
8086 opcode table
8086 opcode
8086 opcode sheet
8086 opcode sheet free download
8086 mnemonic code
8086 mnemonic opcode
intel 8086 opcode sheet
imm32
intel 8086
|
8-bit opcode
Abstract: invalid opcode sahf instruction 0F21 0F20-0F24 BT 3713
Text: Opcode Map 37 The opcode tables in this chapter are provided to aid in interpreting Intel Architecture object code. The instructions are divided into three encoding groups: 1-byte opcode encodings, 2-byte opcode encodings, and escape floating-point encodings. The 1- and 2-byte opcode encodings are used to
|
Original
|
PDF
|
|
8086 opcode machine code
Abstract: 8086 opcode sheet 8086 mnemonic code 8086 opcode sheet free download 8086 interrupt vector table 8086 mnemonic opcode 8086 opcode sheet int intel 8086 opcode sheet 8086 OPCODE DATA SHEET CACHE MEMORY FOR 8086
Text: I 47 I 47.1 IDIV—Signed Divide Opcode Instruction Description F6 /7 IDIV r/m8 Signed divide AX where AH must contain signextension of AL by r/m byte. (Results: AL=Quotient, AH=Remainder) F7 /7 IDIV r/m16 Signed divide DX:AX (where DX must contain signextension of AX) by r/m word. (Results: AX=Quotient,
|
Original
|
PDF
|
r/m16
r/m32
Virtual-8086
8086 opcode machine code
8086 opcode sheet
8086 mnemonic code
8086 opcode sheet free download
8086 interrupt vector table
8086 mnemonic opcode
8086 opcode sheet int
intel 8086 opcode sheet
8086 OPCODE DATA SHEET
CACHE MEMORY FOR 8086
|
8086 opcode sheet
Abstract: opcode table for 8086 8086 opcode 8086 opcode table intel 8086 INSTRUCTION SET 8086 opcode sheet free download intel 8086 opcode sheet 8086 flags 8086 OPCODE DATA SHEET segment register
Text: V 58 V 58.1 VERR, VERW—Verify a Segment for Reading or Writing Opcode Instruction Description 0F 00 /4 VERR r/m16 Set ZF=1 if segment specified with r/m16 can be read 0F 00 /5 VERW r/m16 Set ZF=1 if segment specified with r/m16 can be written Description
|
Original
|
PDF
|
r/m16
r/m16
16-bit
Virtual-8086
8086 opcode sheet
opcode table for 8086
8086 opcode
8086 opcode table
intel 8086 INSTRUCTION SET
8086 opcode sheet free download
intel 8086 opcode sheet
8086 flags
8086 OPCODE DATA SHEET
segment register
|
IBM25PPC750GX
Abstract: IBM PPC750 EB02 IBM25PPC750 ppc750 ppc7
Text: PowerPC 750 RISC Microprocessor Family Part Number Specific Information This supplement contains information pertinent to the IBM PowerPC 750TM RISC microprocessor family. Part Number Specific Information for Revision D and Revision E An electrical noise sensitivity during random opcode testing in the factory on some IBM25PPC750–DB02660/
|
Original
|
PDF
|
750TM
IBM25PPC750
DB02660/
EB02660
DB02330/IBM25PPC750
EB02330
IBM25PPC750GX
IBM PPC750
EB02
ppc750
ppc7
|
MC9S12C32FS
Abstract: MC9S12C32 M68MOD912C32 bosch pump an2255 lqfp 52 68HC11 68HC12 9S12DP256BDGV2 HCS12
Text: 16-bit Microcontrollers MC9S12C32 Target Applications > Automotive applications Features Benefits High-Performance 16-bit HCS12 CPU Core > Industrial control > 25 MHz bus operation at 3.3V to 5V for 40 ns minimum instruction cycle time > Opcode compatible with the 68HC11
|
Original
|
PDF
|
16-bit
MC9S12C32
HCS12
68HC11
68HC12
68HC12
MC9S12C32FS
MC9S12C32FS
MC9S12C32
M68MOD912C32
bosch pump
an2255
lqfp 52
68HC11
9S12DP256BDGV2
|
HCS12
Abstract: MC9S12DP256 68hc12 motorola linker 9S12DP256BDGV2 S12DP256PIMV2 USBMULTILINKBDM MC9S12DT256 Freescale 68HC11 SPI Block Guide 68HC11
Text: 16-bit Microcontrollers MC9S12DT256 Target Applications Features > Automotive applications High-Performance 16-bit HCS12 CPU Core > Industrial control > 25 MHz bus operation at 5V for 40 ns minimum instruction cycle time Benefits > Opcode compatible with the 68HC11
|
Original
|
PDF
|
16-bit
MC9S12DT256
HCS12
68HC11
68HC12
68HC12
MC9S12DT256
DT256
MC9S12DP256
68hc12 motorola linker
9S12DP256BDGV2
S12DP256PIMV2
USBMULTILINKBDM
Freescale 68HC11
SPI Block Guide
68HC11
|
|
|
Untitled
Abstract: No abstract text available
Text: P5CD072 Secure Dual Interface PKI Smart Card Controller Rev. 1.2 — 4 October 2004 Short Form Specification 1. General description 1.1 Family description Philips Semiconductors SmartMX Memory eXtension multiple interface option platform features a significantly enhanced smart card IC architecture. New powerful opcodes are
|
Original
|
PDF
|
P5CD072
80C51
|
Untitled
Abstract: No abstract text available
Text: P5SC036 Secure Smart Card Controller Rev. 1.2 — 2004 April 14 Short Form Specification 1. General description 1.1 Family description Philips Semiconductors SmartMX Memory eXtension multiple interface option platform features a significantly enhanced smart card IC architecture. New powerful opcodes are
|
Original
|
PDF
|
P5SC036
80C51
|
Untitled
Abstract: No abstract text available
Text: P5CC072 Secure PKI Smart Card Controller Rev. 1.0 — 14 April 2004 Short Form Specification 1. General description 1.1 Family description Philips Semiconductors SmartMX Memory eXtension multiple interface option platform features a significantly enhanced smart card IC architecture. New powerful opcodes are
|
Original
|
PDF
|
P5CC072
80C51
|
Philips Mifare
Abstract: MIFARE Software
Text: P5CD036 Secure Dual Interface PKI Smart Card Controller Rev. 1.1 — 2004 August 27 Short Form Specification 1. General description 1.1 Family description Philips Semiconductors SmartMX Memory eXtension multiple interface option platform features a significantly enhanced smart card IC architecture. New powerful opcodes are
|
Original
|
PDF
|
P5CD036
80C51
Philips Mifare
MIFARE Software
|
microchip application note
Abstract: motorola hc08 motorola hc08 datasheet DS00617 PIC18 c compiler sleep hc08 can bus AN617 DK-2750 HC08 PIC16
Text: TB071 Converting from Motorola HC08 to Microchip Assembler: A Quick Reference Author: Rodger Richey Microchip Technology Inc. When migrating assembly language programs from one family of microcontrollers to another, the first question is almost always: “What’s the equivalent opcode?”
|
Original
|
PDF
|
TB071
DK-2750
D-85737
DS91071A-page
microchip application note
motorola hc08
motorola hc08 datasheet
DS00617
PIC18 c compiler sleep
hc08 can bus
AN617
HC08
PIC16
|
qx25
Abstract: No abstract text available
Text: PIC16C9XX 15.0 INSTRUCTION SET SUMMARY Each PIC16CXXX instruction is a 14-bit word divided into an OPCODE which specifies the instruction type and one or more operands which further specify the operation of the instruction. The PIC16CXX instruction set summary in Table 15-2 lists byte-oriented, bit-oriented, and literal and control operations. Table 15-1
|
OCR Scan
|
PDF
|
PIC16C9XX
PIC16CXXX
14-bit
PIC16CXX
DS30444E
qx25
|
TL SK 100B
Abstract: ORD 1114 PA-L19
Text: 10 A l p h a I ns t r uc t i on S u m m a r y This section contains a sum m ary of all Alpha architecture instructions. All values are in hexadecimal radix. Table 51 describes the contents of the Format and Opcode columns that are in Table 52. T a b l e 51
|
OCR Scan
|
PDF
|
11-bit
16-bit
26-bit
TL SK 100B
ORD 1114
PA-L19
|
ORD 1114
Abstract: 7817A
Text: 10 Alpha Instruction Summary This section contains a summary of all Alpha architecture instructions. All values are in hexadecim al radix Table 15 describes the contents of the Format and Opcode columns that are in Table 16. Table 15 Instruction Format and Opcode Notation
|
OCR Scan
|
PDF
|
11-bit
16-bit
26-bit
ORD 1114
7817A
|
OPC07
Abstract: opcoa 1702D SVC 561 10 OPC02 BIC 1222 1702b SVC 561 -10 OB2223
Text: 10 Alpha Instruction Summary This section contains a summary of all Alpha architecture instructions. All values are in hexadecimal radix. Table 15 describes the contents of the Format and Opcode col umns that are in Table 16. Table 15 Instruction Format and Opcode Notation
|
OCR Scan
|
PDF
|
11-bit
16-bit
26-bit
OPC07
opcoa
1702D
SVC 561 10
OPC02
BIC 1222
1702b
SVC 561 -10
OB2223
|
Untitled
Abstract: No abstract text available
Text: 10.0 Programming of the Keyboard Controller The PC87323 keyboard controller is 100% opcode compati ble with the 8042 microcontroller. It uses 93 instructions, most of which are single-byte instructions. The rest are 2byte instructions. Instruction execution times range from 1
|
OCR Scan
|
PDF
|
PC87323
28-2F
98-9B
08-0B
88-8B
38-3B
14-F4
|