S-CPGA-P181
Abstract: No abstract text available
Text: MECHANICAL DATA MCPG020 – NOVEMBER 1995 GE S-CPGA-P181 CERAMIC PIN GRID ARRAY 1.590 (40,40) SQ 1.148 (37,60) 1.400 (35,56) TYP 0.100 (2,54) TYP R P N M L K J H G F E D C B A 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0.185 (4,70) 0.140 (3,55) 0.060 (1,52) 0.040 (1,02)
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MCPG020
S-CPGA-P181)
4073425/A
S-CPGA-P181
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texas instruments 1148
Abstract: No abstract text available
Text: MECHANICAL DATA MCPG020 – NOVEMBER 1995 GE S-CPGA-P181 CERAMIC PIN GRID ARRAY PACKAGE 1.590 (40,40) SQ 1.148 (37,60) 1.400 (35,56) TYP 0.100 (2,54) TYP R P N M L K J H G F E D C B A 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0.185 (4,70) 0.140 (3,55) 0.060 (1,52)
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MCPG020
S-CPGA-P181)
4073425/A
texas instruments 1148
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Untitled
Abstract: No abstract text available
Text: MECHANICAL DATA MCPG014 – OCTOBER 1995 GB S-CPGA-P181 CERAMIC PIN GRID ARRAY 1.590 (40,40) SQ 1.148 (37,60) 1.400 (35,56) TYP 0.100 (2,54) TYP R P N M L K J H G F E D C B A 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0.185 (4,70) 0.140 (3,55) 0.055 (1,40) 0.045 (1,14)
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MCPG014
S-CPGA-P181)
4073426/A
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p181 gb
Abstract: P181
Text: MECHANICAL DATA MCPG014 – OCTOBER 1995 GB S-CPGA-P181 CERAMIC PIN GRID ARRAY PACKAGE 1.590 (40,40) SQ 1.148 (37,60) 1.400 (35,56) TYP 0.100 (2,54) TYP R P N M L K J H G F E D C B A 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0.185 (4,70) 0.140 (3,55) 0.055 (1,40)
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MCPG014
S-CPGA-P181)
4073426/A
p181 gb
P181
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p181 gb
Abstract: S-CPGA-P181 p181 P181 pdf datasheet
Text: MECHANICAL DATA MCPG014 – OCTOBER 1995 GB S-CPGA-P181 CERAMIC PIN GRID ARRAY 1.590 (40,40) SQ 1.148 (37,60) 1.400 (35,56) TYP 0.100 (2,54) TYP R P N M L K J H G F E D C B A 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0.185 (4,70) 0.140 (3,55) 0.055 (1,40) 0.045 (1,14)
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MCPG014
S-CPGA-P181)
4073426/A
p181 gb
S-CPGA-P181
p181
P181 pdf datasheet
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PDF
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P181 GB
Abstract: p181
Text: MECHANICAL DATA MCPG014A – FEBRUARY 1996 – REVISED JANUARY 2002 GB S-CPGA-P181 CERAMIC PIN GRID ARRAY 1.590 (40,40) SQ 1.560 (39,62) 1.400 (35,56) TYP 0.100 (2,54) TYP R P N M L K J H G F E D C B A A1 Corner 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Bottom View
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MCPG014A
S-CPGA-P181)
4073426/C
P181 GB
p181
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J29 P190
Abstract: L-29 p302 transistor p98 p115 p106 P191 transistor be p88 P142 P143
Text: XC4000XLA/XV Field Programmable Gate Arrays January 28, 1999 Version 1.0 0* R XC4000XLA/XV Field Programmable Gate Arrays XC4000XLA Family Field Programmable Gate Arrays Package Pinouts XC4013XLA Pinout Table XC4013XLA Pinout Table (Continued) XC4013XLA Pinout Table
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XC4000XLA/XV
XC4000XLA
XC4013XLA
PQ160
PQ208
PQ240
BG256
J29 P190
L-29
p302
transistor p98
p115
p106
P191
transistor be p88
P142
P143
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j29 p190
Abstract: AK29 BG35 n4 p69 XC4020XLA
Text: XC4000XLA/XV Field Programmable Gate Arrays January 28, 1999 Version 1.0 0* R XC4000XLA/XV Field Programmable Gate Arrays XC4000XLA Family Field Programmable Gate Arrays Package Pinouts XC4013XLA Pinout Table XC4013XLA Pinout Table (Continued) XC4013XLA Pinout Table
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XC4000XLA/XV
XC4000XLA
XC4013XLA
PQ160
XC4085XLA
HQ160
HQ208
j29 p190
AK29
BG35
n4 p69
XC4020XLA
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P239
Abstract: P181 P185 P-239 P212 P213 p178 P215 P216 P218
Text: XC4025 and XC4025E Pinout Table Pin Name VCC I/O A8 I/O(A9) I/O I/O I/O I/O I/O(A10) I/O(A11) I/O I/O I/O I/O VCC I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O(A12) I/O(A13) I/O I/O I/O I/O I/O I/O I/O(A14) SGCK1(A15;I/O) VCC GND PGCK1(A16;I/O) I/O(A17)
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XC4025
XC4025E
PG223
MQ240
PG299
HQ304
P239
P181
P185
P-239
P212
P213
p178
P215
P216
P218
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n4 p69
Abstract: v1 j p304 MQ240 P212 P213 P214 P215 PG223 XC4025 XC4025E
Text: Xilinx Common Package Footprints BG225 225-Pin Ball Grid Array XC4010BG225 (Bottom View) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R VCC PGCK2 (I/O) I/O I/O I/O I/O I/O VCC I/O N.C. I/O I/O I/O I/O VCC P SGCK2 (I/O) M0 I/O (HDC) I/O (LDC) N.C. I/O N.C. I/O (/INIT)
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BG225
225-Pin
XC4010BG225
PG299
HQ304
PG223
MQ240
n4 p69
v1 j p304
MQ240
P212
P213
P214
P215
PG223
XC4025
XC4025E
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AF2.5 din 74
Abstract: P83 T15 J955 XC4028EX pinout 61.35 9 257 J29 P190 transistor p98 PC84 PG120 VQ100
Text: R XC4000E and XC4000X Series Field Programmable Gate Arrays Device-Specific Pinout Tables Device-specific tables include all packages for each XC4000 and XC4000X Series device. They follow the pad locations around the die, and include boundary scan register locations.
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XC4000E
XC4000X
XC4000
XC4002XL
XC4002XL
DS006
AF2.5 din 74
P83 T15
J955
XC4028EX pinout
61.35 9 257
J29 P190
transistor p98
PC84
PG120
VQ100
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AF2.5 din 74
Abstract: P181 Japan K2808 634 p181 715 P181 K1805 J29 P190 xc4005e-TQ144 499 P44 20 g8 p281
Text: XC4000E and XC4000X Series Field Programmable Gate Arrays November 10, 1997 Version 1.4 4 Device-Specific Pinout Tables Device-specific tables include all packages for each XC4000 and XC4000X Series device. They follow the pad locations around the die, and include boundary scan register locations.
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XC4000E
XC4000X
XC4000
XC4003E
XC4003E
AF2.5 din 74
P181 Japan
K2808
634 p181
715 P181
K1805
J29 P190
xc4005e-TQ144
499 P44 20
g8 p281
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Untitled
Abstract: No abstract text available
Text: Product Obsolete/Under Obsolescence R XC4000E and XC4000X Series Field Programmable Gate Arrays Device-Specific Pinout Tables Device-specific tables include all packages for each XC4000 and XC4000X Series device. They follow the pad locations around the die, and include boundary scan register locations.
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XC4000E
XC4000X
XC4000
XC4002XL
XC4002XL
BG256
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P331
Abstract: p181 P086 p323 P085 P237 p044 p055 P084 P005
Text: 5 6 7 GND UVCC3 GND VCC3C GND 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 VSS5 MD_2 MD_1 X0 X1 VSS5 X1A X0A MD_0 P16_1/PPG9 P16_0/PPG8 P20_6/SCK3/FRCK3 P20_5/SOT3 P20_4/SIN3 P20_2/SCK2/FRCK2 P20_1/SOT2 P20_0/SIN2 P24_7/INT7
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2/AN10
3/AN11
4/AN12
4/SDA0/INT14
PB-91464A-NLS-100PMC
PB-91464A-NLS-100PMC
P331
p181
P086
p323
P085
P237
p044
p055
P084
P005
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Untitled
Abstract: No abstract text available
Text: IDT72401 IDT72402 IDT72403 IDT72404 CMOS PARALLEL FIFO 64 x 4 and 64 x 5 IDT72404 are asynchronous high-performance First-ln/First-Out memories organized as 64 words by 5 bits. The IDT72403 and IDT72404 also have an Output Enable OE pin. The FlFOs accept 4-bit or 5-bit data at the data input
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IDT72401
IDT72402
IDT72403
IDT72404
IDT72401/72403)
IDT72402/72404)
175mW
45MHz
IDT72403/72404
MlL-STD-883,
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J29 P190
Abstract: p239 P116 Diode XC4028XLT XC4062XLT XC4013XLT diode P113 DIODE AJ22 AK19 diode P181
Text: XC4000XLT Family Field Programmable Gate Arrays December 10, 1997 Version 0.8 4* Advance Product Specification XC4000XLT Features XC4000XLT Electrical Features Note: This data sheet describes the XC4000XLT Family devices. This information does not necessarily apply to the
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XC4000XLT
XC4000,
XC4000A,
XC4000D,
XC4000H,
XC4000L,
XC4000E,
J29 P190
p239
P116 Diode
XC4028XLT
XC4062XLT
XC4013XLT
diode P113
DIODE AJ22
AK19 diode
P181
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p181 g8
Abstract: 105 p180 g8 p27m2 L2251 SPARTAN-II xc2s200 pq208 p180 g8 6p114 DS001-4 g5209 N2407
Text: Spartan-II 2.5V FPGA Family: Pinout Tables R DS001-4 v2.0 September 18, 2000 Preliminary Product Specification Pin Definitions Pin Name Dedicated Pin Direction Description GCK0, GCK1, GCK2, GCK3 No Input Clock input pins that connect to Global Clock Buffers. These pins become
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DS001-4
IndicatesP10
DS001-1,
DS001-2,
DS001-3,
DS001-4,
p181 g8
105 p180 g8
p27m2
L2251
SPARTAN-II xc2s200 pq208
p180 g8
6p114
DS001-4
g5209
N2407
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105 p180 g8
Abstract: SPARTAN-II xc2s200 pq208 p181 g8 g5209 p115 SPARTAN XC2S50 P120 G8 transistor be p88 P137 P141
Text: 028 Spartan-II 2.5V FPGA Family: Pinout Tables R DS001-4 v2.5 September 3, 2003 Product Specification Pin Definitions Pin Name Dedicated Pin Direction Description GCK0, GCK1, GCK2, GCK3 No Input Clock input pins that connect to Global Clock Buffers. These pins become
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DS001-4
XC2S50
XC2S30
DS001-1,
DS001-2,
DS001-3,
DS001-4,
105 p180 g8
SPARTAN-II xc2s200 pq208
p181 g8
g5209
p115
SPARTAN XC2S50
P120 G8
transistor be p88
P137
P141
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p181 g8
Abstract: 105 p180 g8 707 p181 g5209 p115 SPARTAN XC2S50 SPARTAN-II xc2s200 pq208 tms 374 transistor be p88 P140
Text: Spartan-II 2.5V FPGA Family: Pinout Tables R DS001-4 v2.4 April 30, 2001 Preliminary Product Specification Pin Definitions Pin Name Dedicated Pin Direction Description GCK0, GCK1, GCK2, GCK3 No Input Clock input pins that connect to Global Clock Buffers. These pins become
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DS001-4
tha00
XC2S50
DS001-1,
DS001-2,
DS001-3,
DS001-4,
p181 g8
105 p180 g8
707 p181
g5209
p115
SPARTAN XC2S50
SPARTAN-II xc2s200 pq208
tms 374
transistor be p88
P140
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p181 4 pin
Abstract: J442 P181 G
Text: PACKAGE DIAGRAMS D48-1 48 pin Sidebraze 2 370 2.430 t .550 .610 * 2^~—' / ^eatingplane^ T ' ' ^ f - 4 022 J32-1 nnnnnnn19 18 17 16 15 ' 30 31 32 1 2 3 UUUUUUUf 045X45° - 450 ; 003 - - 490 i 005 - I , °590
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D48-1
J32-1
nnnnnnn20
045X45°
J44-1
S28-5
S32-1
V28-1
Z20-1
p181 4 pin
J442
P181 G
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p181 4 pin
Abstract: 511000 dram S511000 TC 511000
Text: MOSEL_MS511000 may isso 1,048,576 x 1 Fast Page Mode CMOS Dynamic RAM FEATURES GENERAL DESCRIPTION • Available in 70/80/100/120 ns The M O SEL M S511000 is a CM OS dynam ic RAM organized as 1,048,576 w ords x 1 bit. The M S511000 has been designed for m ainfram e, buffer memory,
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OCR Scan
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S511000
PID0061
MS511000
MS511000-70PC
MS511000-70SC
MS511000-70ZC
MS511000-80PC
MS511000-80SC
MS511000-80ZC
p181 4 pin
511000 dram
TC 511000
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Untitled
Abstract: No abstract text available
Text: MOSEL M S511000 1,048,576 x 1 Fast Page Mode CMOS Dynamic RAM F E A TU R ES G E N E R A L D E S C R IP TIO N • Available in 70/80/100/120 ns The MOSEL MS511000 is a CMOS dynamic RAM organized as 1,048,576 words x 1 bit. The MS511000 has been designed for mainframe, buffer memory,
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OCR Scan
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S511000
MS511000
MS511000
MS511000-70PC
P18-1
MS511000-70SC
S26-1
MS511000-70ZC
Z20-1
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P181 G
Abstract: DRAM 511000-70 ss1891 p181 4 pin 511000-70
Text: MOSEL M S511000 1,048,576 x 1 Fast Page Mode CMOS Dynamic RAM FEATURES GENERAL DESCRIPTION • Available in 70/80/100/120 ns The MOSEL MS511000 is a CMOS dynamic RAM organized as 1,048,576 words x 1 bit. The MS511000 has been designed for mainframe, buffer memory,
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OCR Scan
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S511000
MS511000
PID0061
MS511000
MS511000-70PC
MS511000-70SC
MS511000-70ZC
MS511000-80PC
MS511000-80SC
P181 G
DRAM 511000-70
ss1891
p181 4 pin
511000-70
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PJ87
Abstract: diode pj87 diode p115 P116 Diode P119H DIODE AH10 DIODE AJ15 J29 P190 P128J
Text: £ XILINX XC4000XLT Family Field Programmable Gate Arrays December 10, 1997 Version 0.8 Advance Product Specification XC4000XLT Features XC4000XLT Electrical Features Note: This data sheet describes the XC4000XLT Family devices. This information does not necessarily apply to the
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OCR Scan
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XC4000XLT
XC4000,
XC4000A,
XC4000D,
XC4000H,
XC4000L,
XC4000E,
XC4000EX,
PJ87
diode pj87
diode p115
P116 Diode
P119H
DIODE AH10
DIODE AJ15
J29 P190
P128J
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