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Amphenol ProLabs C-QPASIN-AOC10M Palo Alto Networks PAN-QSFP-AOC-
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DigiKey	C-QPASIN-AOC10M				1	1 $468.75 10 $468.75 100 $445.3125 1000 $468.75 10000 $468.75	Buy Now
Amphenol ProLabs C-SHPASIN-PDAC1M HP 487652-B21 to Intel XDACBL1M
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DigiKey	C-SHPASIN-PDAC1M				1	1 $27.5 10 $27.5 100 $26.125 1000 $27.5 10000 $27.5	Buy Now
Amphenol ProLabs C-SHPASIB-PDAC3M HP 487655-B21 to IBM 90Y9430 Com
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DigiKey	C-SHPASIB-PDAC3M				1	1 $29.75 10 $29.75 100 $28.2625 1000 $29.75 10000 $29.75	Buy Now
Amphenol ProLabs C-SHPASIB-PDAC1M HP 487652-B21 to IBM 90Y9427 Com
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DigiKey	C-SHPASIB-PDAC1M				1	1 $27.5 10 $27.5 100 $26.125 1000 $27.5 10000 $27.5	Buy Now
Amphenol ProLabs C-SHPASIB-PDAC5M HP 537963-B21 to IBM 90Y9433 Com
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DigiKey	C-SHPASIB-PDAC5M				1	1 $42.5 10 $42.5 100 $40.375 1000 $42.5 10000 $42.5	Buy Now

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PASI Datasheets (5)

Part	Manufacturer	Description	Datasheet Type	PDF
pASIC1	QuickLogic	Military 5.0V Very-High-Speed CMOS FPGA	Original	PDF
pASIC 1 Family	Unknown	ViaLink Technology	Original	PDF
pASIC 2 FPGA FAMILY	Unknown	Combining Speed, Density, Low Cost and Flexibility	Original	PDF
pASIC3	QuickLogic	60,000 Usable PLD Gate FPGA Combining High Performance and High Density	Original	PDF
pASIC 3 FPGA Family Data Sheet	Unknown	Up to 60,000 Usable PLD Gate pASIC 3 FPGA Combining High	Original	PDF

PASI Datasheets Context Search

Catalog Datasheet	MFG & Type	Document Tags	PDF
QL3004 Abstract: PLCC-84 QL3060 QL2003 QL2005 QL2007 QL2009 QL3012 QL3025 QL3040 Text: QuickSheet#4 pASIC FPGA Families High-Speed, Low Power, Instant-On, High Security FPGAs pASIC Family Highlights High performance over 400 MHz 100% routability and pin stability Instant-On capability High security and reliability Low power	Original	400MHz QL1004-U1 1210JHGDA QL3004 PLCC-84 QL3060 QL2003 QL2005 QL2007 QL2009 QL3012 QL3025 QL3040	PDF
QL3012 Abstract: PF100 PF144 PL84 QL3012-1PF100C QL3012-1PQ144C Text: QL3012 - pASIC 3 FPGATM 12,000 Usable PLD Gate pASIC 3 FPGA Combining High Performance and High Density QL3012 - pASIC 3 FPGA DEVICE HIGHLIGHTS Device Highlights High Performance & High Density • 12,000 Usable PLD Gates with 118 I/Os ■ 16-bit counter speeds over 300 MHz, data path speeds over	Original	QL3012 16-bit PF100 PF144 PL84 QL3012-1PF100C QL3012-1PQ144C	PDF
Untitled Abstract: No abstract text available Text: QL2009  3.3V and 5.0V pASIC 2 FPGA Combining Speed, Density, Low Cost and Flexibility Rev. C pASIC 2 HIGHLIGHTS Ultimate Verilog/VHDL Silicon Solution -Abundant, high-speed interconnect eliminates manual routing -Flexible logic cell provides high efficiency and performance	Original	QL2009	PDF
16X24B Abstract: CF160 PF100 PF144 PL84 CPGA Package Diagram Text: QL16x24B pASIC 1 Family Very-High-Speed CMOS FPGA Rev C pASIC HIGHLIGHTS …4,000 usable ASIC gates, 122 I/O pins Very High Speed – ViaLink metal-to-metal programmable–via antifuse technology, allows counter speeds over 150 MHz and logic cell delays of under 2 ns.	Original	QL16x24B 16-by-24 84-pin 100-pin 144-pin 160-pin 16-bit 16x24B CF160 PF100 PF144 PL84 CPGA Package Diagram	PDF
PL84 Abstract: ql16x24bl PF100 PF144 Text: QL16x24BL pASIC 1 Family Low Power 3.3 Volt Operation FPGA pASIC HIGHLIGHTS High Speed – ViaLink metal-to-metal programmable–via antifuse technology, allows counter speeds over 80 MHz at 3.3 Volt operation. 5V Tolerant I/Os – Support interface to 5 Volt CMOS, NMOS and	Original	QL16x24BL 16-by-24 84-pin 100-pin 144-pin QL16x24B QL16x24 16x24BL PF144 84-pin PL84 ql16x24bl PF100	PDF
QL4090 Abstract: pASIC 1 Family 160CQFP 208-CQFP Text: QL16x24B pASIC 1 Family Very-High-Speed CMOS FPGA Rev C pASIC HIGHLIGHTS …4,000 usable ASIC gates, 122 I/O pins Very High Speed – ViaLink metal-to-metal programmable–via antifuse technology, allows counter speeds over 150 MHz and logic cell delays of under 2 ns.	Original	QL16x24B 16-by-24 84-pin 100-pin 144-pin 160-pin 16-bit V144-TQFP QL24x32B QL4090 pASIC 1 Family 160CQFP 208-CQFP	PDF
Untitled Abstract: No abstract text available Text: QL3040 pASIC 3 FPGA Data Sheet •••••• 40,000 Usable PLD Gate pASIC 3 FPGA Combining High Performance and High Density Device Highlights High Performance & High Density • 40,000 Usable PLD Gates with 252 I/Os • 300 MHz 16-bit Counters, 400 MHz Datapaths	Original	QL3040 16-bit	PDF
208CQFP Abstract: No abstract text available Text: QL2007  3.3V and 5.0V pASIC 2 FPGA Combining Speed, Density, Low Cost and Flexibility Rev. E pASIC 2 HIGHLIGHTS Ultimate Verilog/VHDL Silicon Solution -Abundant, high-speed interconnect eliminates manual routing -Flexible logic cell provides high efficiency and performance	Original	QL2007 -16-bit l144-TQFP QL24x32B 208-PQFP 208-CQFP 125oC MIL-STD-883 208CQFP	PDF
Untitled Abstract: No abstract text available Text: QL3004 pASIC 3 FPGA Data Sheet •••••• 4,000 Usable PLD Gate pASIC 3 FPGA Combining High Performance and High Density Device Highlights High Performance & High Density • 4,000 Usable PLD Gates with 82 I/Os • 300 MHz 16-bit Counters, 400 MHz Datapaths	Original	QL3004 16-bit	PDF
Untitled Abstract: No abstract text available Text: QL3012 - pASIC 3 FPGATM 12,000 Usable PLD Gate pASIC 3 FPGA Combining High Performance and High Density last updated 5/17/2000 QL3012 - pASIC 3 FPGA DEVICE HIGHLIGHTS Device Highlights High Performance & High Density • 12,000 Usable PLD Gates with 118 I/Os	Original	QL3012 16-bit	PDF
208-PIN Abstract: 456-PIN Text: QL3060 - pASIC 3 FPGATM 60,000 Usable PLD Gate pASIC 3 FPGA Combining High Performance and High Density QL3060 - pASIC 3 FPGA DEVICE HIGHLIGHTS Device Highlights Device Highlights High Performance & High Density • 60,000 Usable PLD Gates with 316 I/Os ■ 16-bit counter speeds over 300 MHz, data path speeds over	Original	QL3060 16-bit 208-PIN 456-PIN	PDF
84-PIN Abstract: PF144 PL84 PQ208 QL2007 QL2007-1PF144C QL2007-1PQ208C 208-Pin PQFP Text: QL2007  3.3V and 5.0V pASIC 2 FPGA Combining Speed, Density, Low Cost and Flexibility Rev. E pASIC 2 HIGHLIGHTS Ultimate Verilog/VHDL Silicon Solution -Abundant, high-speed interconnect eliminates manual routing -Flexible logic cell provides high efficiency and performance	Original	QL2007 84-PIN PF144 PL84 PQ208 QL2007 QL2007-1PF144C QL2007-1PQ208C 208-Pin PQFP	PDF
PF144 Abstract: PQ208 QL24X32B-1PQ208C Text: QL24x32B pASIC 1 Family Very-High-Speed CMOS FPGA pASIC HIGHLIGHTS …8,000 usable ASIC gates, 180 I/O pins Very High Speed – ViaLink metal-to-metal programmable–via antifuse technology, allows counter speeds over 150 MHz and logic cell delays of under 2 ns.	Original	QL24x32B 24-by-32 144-pin 208-pin 24x32B PQ208 M/883C PF144 PF144 QL24X32B-1PQ208C	PDF
QL8X12B Abstract: PF100 pASIC 1 Family circuit diagram of Tri-State Buffer using CMOS Text: QL8X12B pASIC 1 Family Very-High-Speed CMOS FPGA Rev B pASIC HIGHLIGHTS Very High Speed – ViaLink metal-to-metal programmable–via antifuse technology, allows counter speeds over 150 MHz and logic cell delays of under 2 ns. …1,000 usable ASIC gates,	Original	QL8X12B 8-by-12 44-pin 68-pin 100-pin 16-bit QL8X12B PF100 pASIC 1 Family circuit diagram of Tri-State Buffer using CMOS	PDF

Untitled Abstract: No abstract text available Text: QL3004 4,000 Usable PLD Gate pASIC 3 FPGA Combining High Performance and High Density Last Updated August 31, 1999 4 pASIC 3 HIGHLIGHTS … 4,000 usable PLD gates, 82 I/O pins High Performance and High Density -4,000 Usable PLD Gates with 82 I/Os -16-bit counter speeds over 300 MHz, data path speeds over 400 MHz	Original	QL3004 -16-bit QL3004	PDF
DG20AA-120 Abstract: JC-45 DG20AA DG20AA120 DG20AA160 DG20AA40 DG20AA80 E76102 Text: DIODE ISOLATED MOLD TYPE DG20AA UL;E76102 M DG20AA is a medium power isolated module diode suitable for wide range of industrial and home elctronics use. DG20AA is highly reliable by glass pasivation. IF AV 20A, VRRM 1600V Tab terminals for easy wiring. K	Original	DG20AA E76102 DG20AA DG20AA40 DG20AA80 DG20AA120 DG20AA160 50Hz/60Hz, DG20AA-120 JC-45 DG20AA120 DG20AA160 DG20AA40 DG20AA80	PDF
QL3004 Abstract: QL3004-1PL68C PF100 PL84 PQ208 QL3012-1PF100C Text: QL3004 pASIC 3 FPGA Data Sheet •••••• 4,000 Usable PLD Gate pASIC 3 FPGA Combining High Performance and High Density Device Highlights High Performance & High Density • 4,000 Usable PLD Gates with 74 I/Os • 300 MHz 16-bit Counters, 400 MHz Datapaths	Original	QL3004 16-bit QL3004-1PL68C PF100 PL84 PQ208 QL3012-1PF100C	PDF
QEMM386 Abstract: on line ups circuit schematic diagram PL84 CD drive schematic CF160 FPGA kit xc3s400-5pq of 208 pins with operating CF100 PB256 PF100 PF144 Text: QuickLogic - Viewlogic Interface User’s Guide Revision 6.0, November 1996 s e i r e e S fic Pro f O us/ w l e P i v ew k r i o v W ork r Fo d W An Copyright Information Copyright 1991-1995QuickLogic Corporation. All Rights Reserved QuickLogic, the QuickLogic logo, pASIC and SpDE are trademarks of QuickLogic	Original	1991-1995QuickLogic QEMM386 VLD024 VLD025 on line ups circuit schematic diagram PL84 CD drive schematic CF160 FPGA kit xc3s400-5pq of 208 pins with operating CF100 PB256 PF100 PF144	PDF
16X24 Abstract: No abstract text available Text: QL16x24B/QL16x24BH WildCat 4000 Very-High-Speed 4K 12K Gate CMOS FPGA Rev B pASIC HIGHLIGHTS B Very High Speed - V iaL ink metal-to-metal program m able-via anti fuse technology, allows counter speeds over 150 MHz and logic cell delays of under 2 ns.	OCR Scan	QL16x24B/QL16x24BH 16-by-24 84pin 100-pin 144-pin 160pin 16-bit QL16x24BH 16X24	PDF
Untitled Abstract: No abstract text available Text: Q L 8X 12B pASIC 1 Family Very-High-Speed CMOS FPGA Rev B pASIC HIGHLIGHTS Very High Speed - ViaLink" metal-to-metal programmable-via antifuse technology, allows counter speeds over 150 MHz and logic cell delays of under 2 ns. . 1,000 usable ASIC gates,	OCR Scan	8-by-12 44-pin 68-pin 100-pin 16-bit	PDF
Untitled Abstract: No abstract text available Text: QL2005L 5,000 Gate pASIC 2 FPGA Low Power 3.3 Volt Operation ADVANCED DATA pASIC 2 HIGHLIGHTS E Low Power 3.3V Operation, 5V Tolerant -3.0 to 3.6 volt supply operation; ultra low standby power -Supports interface to 5V CMOS, NMOS -Fully pin-out and function compatible with the high speed 5.0V product	OCR Scan	QL2005L	PDF
Untitled Abstract: No abstract text available Text: QL16x24B CMOS FPGA WildCat Series Low Power 3.3 Volt Operation ADVANCE DATA 3.3 VOLT pASIC HIGHLIGHTS High Speed pASIC 1 FPGA Architecture - Enables very high performance operation at 3.3 Volts e.g., datapath speed up to 80 MHz at 3.3V . 5 Very low-power operation - Typical Icc is 250\|iA.	OCR Scan	QL16x24B 0Q3D30	PDF
QL2009 Abstract: QL2009-1PB256C QL2009-1PF144C QL2009-1PQ208C TIL405 Text: Q L2009 9,000 Gate pASIC 2 FPGA Com bining Speed, Density, Low Cost and Flexibility PRELIMINARY DA TA pASIC 2 HIGHLIGHTS E Ultimate Verilog/VHDL Silicon Solution -Abundant, high-speed interconnect eliminates manual routing -Flexible logic cell provides high efficiency and performance	OCR Scan	QL2009 QL2009 PQ208 PF144 144-pin PQ208 208-pin PB256 256-pin 0000b77 QL2009-1PB256C QL2009-1PF144C QL2009-1PQ208C TIL405	PDF
cadence xa 125 2 Abstract: PQ208 QL2009 QL2009-1PB256C QL2009-1PF144C QL2009-1PQ208C IOG20 Text: QL2009 9,000 Gate 3.3V and 5.0V pASIC 2 FPGA Combining Speed, Density, Low Cost and Flexibility PRELIM INARY DATA pASIC 2 HIGHLIGHTS Rev. B 5 Ultimate Verilog/VHDL Silicon Solution -Abundant, high-speed interconnect eliminates manual routing -Flexible logic cell provides high efficiency and performance	OCR Scan	QL2009 QL2009 cadence xa 125 2 PQ208 QL2009-1PB256C QL2009-1PF144C QL2009-1PQ208C IOG20	PDF

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Amphenol ProLabs C-QPASIN-AOC10M

Amphenol ProLabs C-SHPASIN-PDAC1M

Amphenol ProLabs C-SHPASIB-PDAC3M

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PASI Datasheets (5)

PASI Datasheets Context Search

QL3004

QL3012

Untitled

16X24B

PL84

QL4090

Untitled

208CQFP

Untitled

Untitled

208-PIN

84-PIN

PF144

QL8X12B

Untitled

DG20AA-120

QL3004

QEMM386

16X24

Untitled

Untitled

Untitled

QL2009

cadence xa 125 2