Untitled
Abstract: No abstract text available
Text: Signetics 82S153A PLS153A Field Programmable Logic Array (18x42x10) Military Customer Specific Products Signetics Programmable Logic Product Specification PIN CONFIGURATION DESCRIPTION FEATURES The 82S153A is a two-level logic element, consisting of 42 A N D gates and 10 O R
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82S153A
PLS153A)
18x42x10)
82S153A
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26 SIGNETICS
Abstract: No abstract text available
Text: S ig n e t ic s PLS173 Field-Programmable Logic Array 22x42x10 Military Application Specific Products Slgnetlcs Programmable Logic Product Specification PIN CONFIGURATION DESCRIPTION FEATURES The PLS173 is a two-level logic element consisting of 42 AND gates and 10 OR
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PLS173
22x42x10)
PLS173
26 SIGNETICS
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L5472
Abstract: L2688 L5568
Text: r x / i r * ! MICROELECTRONICS XL78C800 Multi-Level E2PLDs PIN CONFIGURATION FEATURES • ■ ■ CLK/I [ Advanced ERASIC Architecture — True gate array style logic integration — From 1 to 42 internal logic levels without using a pin — Eliminates 2-level logic restriction of
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XL78C800
L5472
L2688
L5568
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Untitled
Abstract: No abstract text available
Text: MITSUBISHI ASTTLs pS?< M74AS20P DUAL 4 -INPUT POSITIVE NAND G ATE DESCRIPTION PIN CONFIGURATION TOP VIEW The M74AS20P is a semiconductor integrated circuit consisting of two 4-input positive-logic NAND gates, us able as negative-logic NOR gates. FEATURES
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M74AS20P
M74AS20P
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74AS1804
Abstract: No abstract text available
Text: MITSUBISHI ASTTLs -*00°° M 74AS1804P HEX 2-INPUT NAND DRIVER DESCRIPTION The M74AS1804P is a semiconductor integrated circuit consisting of six 2-input positive-logic NAND buffer gates, usable as negative-logic NOR buffer gates. PIN CONFIGURATION TOP VIEW
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74AS1804P
M74AS1804P
74AS1804
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74AS1000
Abstract: No abstract text available
Text: MITSUBISHI A STTLs M 74AS1000AP QUADRUPLE 2-INPUT POSITIVE NAND DRIVER DESCRIPTION PIN CONFIGURATION TOP VIEW The M74AS1000AP is a semiconductor integrated circuit consisting of four 2-input positive-logic NAND buffer gates, usable as negative-logic NOR buffer gates.
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74AS1000AP
M74AS1000AP
-----h75
74AS1000
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M74AS02P
Abstract: No abstract text available
Text: MITSUBISHI ASTTLs M74AS02P ŸŸ& 0 QUADRUPLE 2-INPUT POSITIVE NOR GATE DESCRIPTION PIN CONFIGURATION TOP VIEW The M74AS02P is a semiconductor integrated circuit consisting of four 2-input positive-logic NOR gates, us able as negative-logic NAND gates.
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M74AS02P
M74AS02P
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plhs18p8
Abstract: No abstract text available
Text: Signetics PLHS18P8A Programmable AND Array Logic 18x72x8 Military Standard Products Product Specification PIN CONFIGURATION DESCRIPTION FEATURES The PLHS18P8A is a two-level logic ele ment consisting of 72 AND gates and 8 OR gates with fusible connections for pro
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PLHS18P8A
18x72x8)
PLHS18P8A
plhs18p8
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Untitled
Abstract: No abstract text available
Text: PLS173 Slgnetics Field-Programmable Logic Array 22x42x10 Military Application Specific Products Signetics Programmable Logic Product Specification PIN CONFIGURATION DESCRIPTION FEATURES T h e P L S 1 7 3 is a two-level logic elem ent consisting of 4 2 A N D gates and 10 O R
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PLS173
22x42x10)
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Untitled
Abstract: No abstract text available
Text: MITSUBISHI ASTTLs M74AS08P QUADRUPLE 2-INPUT POSITIVE AND GATE DESCRIPTION PIN CONFIGURATION TOP VIEW The M74AS08P is a semiconductor integrated circuit consisting of four 2-input positive-logic AND gates, us able as negative-logic OR gates. FEATURES • High speed
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M74AS08P
M74AS08P
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logic gates pin configuration
Abstract: PLHS18P8A pin configuration of logic gates logic gates pin configuration and
Text: Product specification Signetics Military Standard Products Programmable AND array logic 18 x 72 x 8 PIN CONFIGURATION DESCRIPTION FEATURES The PLHS18P8A is a two-level logic element consisting of 72 AND gates and 8 OR gates with fusible connections for programming I/O
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PLHS18P8A
PLHS18P8A
20-Pin
300mil-wide
PLHS18P8A/BRA
PLHS18P8A/B2A
PLHS18P8A/BSA
logic gates pin configuration
pin configuration of logic gates
logic gates pin configuration and
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plus405
Abstract: pin diagram of TVC 2 HB
Text: PLUS405 Signetics Field-Programmable Logic Sequencer 16x64x8 Military Application Specific Products Signetics Programmable Logic Product Specification • Series 28 PIN CONFIGURATION DESCRIPTION FEATURES The PLUS405 device is a bipolar pro grammable state machine of the Mealy
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PLUS405
PLUS405
16x64x8)
30MHz
PLS105/105A
pin diagram of TVC 2 HB
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plhs18p8
Abstract: PLHS18 PLHS18P8A
Text: Signetics Military Standard Products PLHS18P8A Programmable AND Array Logic 18x72x8 Product Specification PIN CONFIGURATION DESCRIPTION FE A TU R E S The PLHS18P8A is a two-level logic ele ment consisting of 72 ANDgates and SOR gates with fusible connections for pro
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PLHS18P8A
PLHS18P8A
18x72x8)
plhs18p8
PLHS18
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Untitled
Abstract: No abstract text available
Text: MITSUBISHI HIGH S P E E D CMOS M74HC20P M74HC20DP DUAL 4-INPUT POSITIVE NAND GATE DESCRIPTION The M74HC20 is a semiconductor integrated circuit con PIN CONFIGURATION TOP VIEW sisting of two 4-input positive-logic NAND, usable as nega tive-logic NOR gates.
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M74HC20P
M74HC20DP
M74HC20
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M74F00P
Abstract: No abstract text available
Text: i b54Tña7 ODlMOäS E ,*oOo c ' I MITSUBISHI ADVANCED SCHOTTKY TTL M 74F00P/FP/DP niTSUBISHI íDGTL LOGIC} Ó7E t ; QUADRUPLE 2-IN PU T POSITIVE NAND GATE DESCRIPTION PIN CONFIGURATION TOP VIEW The M 74F00P is a semiconductor integrated circuit con sisting of four 2-i'nput positive-logic NAND gates, usable
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74F00P/FP/DP
74F00P
M74F00P*
a--25
--50Q
M74F00P
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Untitled
Abstract: No abstract text available
Text: D E I MITSUBISHI íDGTL LOGIC} TI ^ 2 ^ 0 2 7 1 G D lE lñ b |~ “ MITSUBISHI ASTTLs M74AS32P ,*o O 7-Y3-.SQUADRUPLE 2-INPUT POSITIVE OR GATE DESCRIPTION PIN CONFIGURATION TOP VIEW The M74AS32P is a semiconductor integrated circuit consisting of tour 2-input positive-logic OR gates, us
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M74AS32P
M74AS32P
DD1S17J
20-PIN
24P4D
24-PIN
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G4849
Abstract: No abstract text available
Text: PLUS405 Signetics Field-Programmable Logic Sequencer 16 x 64 x 8 Military Application Specific Products Signetics Programmable Logic Product Specification • Series 28 PIN CONFIGURATION DESCRIPTION FEATURES Th e P LU S 405 device is a bipolar pro gram m able state m achine of the M ealy
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Untitled
Abstract: No abstract text available
Text: GD54/74LS14 HEX SCHMITT-TRIGGER INVERTERS Description Pin Configuration This device contains six independent gates each of which performs the logic INVERT function. Each in put has hysteresis which increases the noise im munity and transforms a slowly changing input signal
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GD54/74LS14
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74LS14 oscillator 4 Mhz
Abstract: 74ls14 pin configuration 74LS14 function table pin configuration 74LS14 74ls14 ttl 74ls14 74LS TTL Oscillator 54LS 74LS IN3064
Text: GD54/74LS14 HEX SCHMITT-TRIGGER INVERTERS Description Pin Configuration This device contains six independent gates each of which performs the logic INVERT function. Each in put has hysteresis which increases the noise im munity and transforms a slowly changing input signal
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GD54/74LS14
IN916
IN3064
74LS14 oscillator 4 Mhz
74ls14 pin configuration
74LS14 function table
pin configuration 74LS14
74ls14 ttl
74ls14
74LS TTL Oscillator
54LS
74LS
IN3064
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PDF
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Untitled
Abstract: No abstract text available
Text: GD54/74LS14 HEX SCHMITT-TRIGGER INVERTERS Description Pin Configuration This device contains six independent gates each of which perforins th logic INVERT function. Each in put has hysteresis which increases the noise im munity and tr&nsfotms a slowly changing Input signal
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GD54/74LS14
402A757
D0D42DÃ
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Untitled
Abstract: No abstract text available
Text: GD54/74S51 DUAL 2-WIDE 2-INPUT AND-OR-INVERT GATES Description Pin Configuration This device contains two independent combinations of gates each of which performs the logic AND-ORINVERT function. MAKE N O EXTERNAL CO NNECTIO N V Cc 1B 1D 1C 1Y Y=AB+C D Function Table
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GD54/74S51
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74ls145
Abstract: No abstract text available
Text: GD54/74LS145 BCD-TO-DECIMAL DECODER/DRIVER Features Pin Configuration • Full Decoding of Input Logic • 80-mA Sink-Current Capability • All Outputs Are Off for Invalid BCD Input Con ditions • Low Power Dissipation of ’LS145.35 mW Typical INPUTS
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GD54/74LS145
80-mA
LS145.
74ls145
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74LS10 mitsubishi
Abstract: No abstract text available
Text: M IT S U B IS H I HIGH SPEED CMOS M74HC10P/FP/DP T R IP L E 3 -IN P U T P O S IT IV E NAND GATE DESCRIPTION PIN CONFIGURATION TOP VIEW The M74HC10 is a semiconductor integrated circuit con sisting of three 3-input positive-logic NAND gates, usable as negative-logic NOR gates.
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M74HC10P/FP/DP
M74HC10
74LSTTL
14P2P
14-PIN
16P2P
16-PIN
20P2V
20-PIN
74LS10 mitsubishi
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Untitled
Abstract: No abstract text available
Text: MITSUBISHI ALSTTLs _ MITSUBI SHI -CDGTL LOGIC} 11 M 74ALS1 0 2 0 AP deJ hSMTaev üaiavati 4 | DUAL 4-IN P U T POSITIVE NAND BUFFER - 7 ^ ' Y 3 ~ / S ’ DESCRIPTION PIN CONFIGURATION TOP VIEW The M74ALS1020AP is a semiconductor integrated cir cuit consisting of two 4-input positive-logic NAND buffer
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74ALS1
M74ALS1020AP
150mil
16P2P
16-PIN
T-90-20
20P2V
20-PIN
300mll
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