Please enter a valid full or partial manufacturer part number with a minimum of 3 letters or numbers

    PIN CONFIGURATION OF LOGIC GATES Search Results

    PIN CONFIGURATION OF LOGIC GATES Result Highlights (5)

    Part ECAD Model Manufacturer Description Download Buy
    TB67H481FTG Toshiba Electronic Devices & Storage Corporation Stepping and Brushed Motor Driver /Bipolar Type / Vout(V)=50 / Iout(A)=3.0 / IN input type / VQFN32 Visit Toshiba Electronic Devices & Storage Corporation
    DCL541A01 Toshiba Electronic Devices & Storage Corporation Digital Isolator / VDD=2.25~5.5V / 150Mbps / 4 channel(F:R=3:1) / Default Output Logic: Low / Input disable Visit Toshiba Electronic Devices & Storage Corporation
    DCL542H01 Toshiba Electronic Devices & Storage Corporation Digital Isolator / VDD=2.25~5.5V / 150Mbps / 4 channel(F:R=2:2) / Default Output Logic: High / Output enable Visit Toshiba Electronic Devices & Storage Corporation
    DCL541B01 Toshiba Electronic Devices & Storage Corporation Digital Isolator / VDD=2.25~5.5V / 150Mbps / 4 channel(F:R=3:1) / Default Output Logic: High / Input disable Visit Toshiba Electronic Devices & Storage Corporation
    DCL542L01 Toshiba Electronic Devices & Storage Corporation Digital Isolator / VDD=2.25~5.5V / 150Mbps / 4 channel(F:R=2:2) / Default Output Logic: Low / Output enable Visit Toshiba Electronic Devices & Storage Corporation

    PIN CONFIGURATION OF LOGIC GATES Datasheets Context Search

    Catalog Datasheet MFG & Type PDF Document Tags

    xc4000 application note

    Abstract: P8202 XCS20 TQ144 XC4000 XCS05 XCS05XL XCS10 XCS10XL 188 p33 Transistor XCS20XL
    Text: Spartan and Spartan-XL Families Field Programmable Gate Arrays R DS060 v1.5 March 2, 2000 Introduction Product Specification • The Spartan series is the first high-volume production FPGA solution to deliver all the key requirements for ASIC replacement up to 40,000 gates. These requirements


    Original     		PDF DS060 XCS20XL-4 PQ208C 100oC) xc4000 application note P8202 XCS20 TQ144 XC4000 XCS05 XCS05XL XCS10 XCS10XL 188 p33 Transistor XCS20XL

    binary tree multipliers

    Abstract: EP1M120 A7B9 A5B13
    Text: Mercury Programmable Logic Device Family January 2003, ver. 2.2 Features… Data Sheet • ■ Table 1. Mercury Device Features Feature Typical gates HSDI channels LEs ESBs 1 Maximum RAM bits Maximum user I/O pins EP1M120 EP1M350 120,000 350,000 8 18


    Original     		PDF EP1M120 EP1M350 binary tree multipliers EP1M120 A7B9 A5B13

    Untitled

    Abstract: No abstract text available
    Text: QL5130 QuickPCI Data Sheet • • • • • • 33 MHz/32-Bit PCI Target with Embedded Programmable Logic and Dual Port SRAM Device Highlights High Performance PCI Controller Programmable Logic • 57 K system gates/619 logic cells • 13,824 RAM bits, up to 157 I/O pins


    Original     		PDF QL5130 Hz/32-Bit 32-bit/33 95/98/2000/NT4 144-pin 208-pin 256-PBGA

    TQ144

    Abstract: XCV100 XCV1000 XCV150 XCV200 XCV300 XCV400 XCV50 XCV600 XCV800
    Text: Virtex 2.5 V Field Programmable Gate Arrays R January 27, 1999 Version 1.2 3* Features • • • • • Advance Product Specification • Fast, high-density Field-Programmable Gate Arrays - Densities from 50k to 1M system gates - System performance up to 200 MHz


    Original     		PDF 66-MHz 16-bit 32-bit XCV150 XCV300 TQ144 XCV100 XCV1000 XCV150 XCV200 XCV400 XCV50 XCV600 XCV800

    EPX880-10

    Abstract: EPX8160-10 EPX8160-12 EPX880-12
    Text: FLASHlogic Programmable Logic Device Family June 1996, ver. 2 Features. Data Sheet • ■ ■ ■ High-performance programmable logic device PLD family – SRAM-based logic with shadow FLASH memory elements fabricated on advanced CMOS technology – Logic densities from 1,600 to 3,200 usable gates (see Table 1)


    Original     		PDF 24V10 84-Pin 132-Pin EPX8160 EPX8160 208-Pin EPX880-10 EPX8160-10 EPX8160-12 EPX880-12

    Z684

    Abstract: MSM13R0000 MSM98R000 pbeb Signal Path Designer Z684-PCI s/z684 bridge
    Text: Z684 PCI Bus Controller 0.5µ m Technology Mega Macrocell DESCRIPTION The PCI Bus Controller Mega Macrocell is a featured element in OKI’s 0.5µm Sea of Gates SOG and Customer Structured Array (CSA) families. Designers can significantly reduce design and simulation effort


    Original     		PDF 486-like Z684 MSM13R0000 MSM98R000 pbeb Signal Path Designer Z684-PCI s/z684 bridge

    74AS1804

    Abstract: No abstract text available
    Text: MITSUBISHI ASTTLs -*00°° M 74AS1804P HEX 2-INPUT NAND DRIVER DESCRIPTION The M74AS1804P is a semiconductor integrated circuit consisting of six 2-input positive-logic NAND buffer gates, usable as negative-logic NOR buffer gates. PIN CONFIGURATION TOP VIEW


    OCR Scan     		PDF 74AS1804P M74AS1804P 74AS1804

    Untitled

    Abstract: No abstract text available
    Text: MITSUBISHI ASTTLs M74AS08P QUADRUPLE 2-INPUT POSITIVE AND GATE DESCRIPTION PIN CONFIGURATION TOP VIEW The M74AS08P is a semiconductor integrated circuit consisting of four 2-input positive-logic AND gates, us­ able as negative-logic OR gates. FEATURES • High speed


    OCR Scan     		PDF M74AS08P M74AS08P

    Untitled

    Abstract: No abstract text available
    Text: D E I MITSUBISHI íDGTL LOGIC} TI ^ 2 ^ 0 2 7 1 G D lE lñ b |~ “ MITSUBISHI ASTTLs M74AS32P ,*o O 7-Y3-.SQUADRUPLE 2-INPUT POSITIVE OR GATE DESCRIPTION PIN CONFIGURATION TOP VIEW The M74AS32P is a semiconductor integrated circuit consisting of tour 2-input positive-logic OR gates, us­


    OCR Scan     		PDF M74AS32P M74AS32P DD1S17J 20-PIN 24P4D 24-PIN

    74ls145

    Abstract: No abstract text available
    Text: GD54/74LS145 BCD-TO-DECIMAL DECODER/DRIVER Features Pin Configuration • Full Decoding of Input Logic • 80-mA Sink-Current Capability • All Outputs Are Off for Invalid BCD Input Con­ ditions • Low Power Dissipation of ’LS145.35 mW Typical INPUTS


    OCR Scan     		PDF GD54/74LS145 80-mA LS145. 74ls145

    Untitled

    Abstract: No abstract text available
    Text: MITSUBISHI ASTTLs M74AS832BP HEX 2-IN PU T OR DRIVER DESCRIPTION The M 74A S 832B P is a sem iconductor integrated circuit PIN CONFIGURATION TOP VIEW consisting of six 2-input positive-logic OR buffer gates, usable as negative-log ic A N D buffer gates.


    OCR Scan     		PDF M74AS832BP --50Q

    Untitled

    Abstract: No abstract text available
    Text: GD54/74LS55 2WIDE 4-INPUT AND-OR-INVERT GATES Description This device contains a combination of gates each of which performs the logic AND-OR-INVERT function. Pin Configuration Vcc H G F E NC Y Y =A BC D+EFG H Function Table Inputs Output A B C D E F G H Y


    OCR Scan     		PDF GD54/74LS55

    Untitled

    Abstract: No abstract text available
    Text: MITSUBISHI ASTTLs M74AS1808P HEX 2-IN PU T AND DRIVER DESCRIPTION The M 7 4A S 1 808 P is a sem iconductor integrated circuit PIN CONFIGURATION TOP VIEW consisting of six 2-input positive-logic A N D buffer gates, usable as n egative-log ic OR buffer gates.


    OCR Scan     		PDF M74AS1808P

    Untitled

    Abstract: No abstract text available
    Text: MITSUBISHI ASTTLs M 74AS1008AP QUADRUPLE 2-INPUT POSITIVE AND DRIVER DESCRIPTION PIN CONFIGURATION TOP VIEW The M 7 4A S 1 008 A P is a sem iconductor integrated circuit consisting of four 2-input positive-logic AND buffer gates, usable as n e g ative-log ic OR buffer gates.


    OCR Scan     		PDF 74AS1008AP

    Untitled

    Abstract: No abstract text available
    Text: GD54/74LS27 TRIPLE 3-INPUT POSITIVE-NOR GATES Description Pin Configuration This device contains three independent gates each of which performs the logic NOR function. ; Y=A+B+C Function V cc u 1Y 3C 3B 3A 3Y 13 12 11 10 9 8 r dble each gate Input 1C Output


    OCR Scan     		PDF GD54/74LS27

    4000B

    Abstract: M74HC4002 M74HC4002P
    Text: M IT S U B IS H I HIGH S P E E D C M O S M 74H C 4002P D U A L 4 -IN P U T P O S IT IV E NOR G ATE DESCRIPTION PIN CONFIGURATION TOP VIEW T h e M 7 4 H C 4 0 0 2 is a sem iconductor in teg ra te d circuit con­ sisting of tw o 4-inp ut po sitive-logic N O R , usable as n e g a ­


    OCR Scan     		PDF M74HC4002P M74HC4002 4000B M74HC4002P

    epf8282 hardware

    Abstract: epf8282 block pf815 EPF81188 PF8150 EPF8282
    Text: FLEX 8000 Programmable Logic Device Family Datasheet August 1993, ver. 3 Features □ □ □ □ □ □ □ □ □ □ □ □ High-density, register-rich programmable logic device family 2,500 to 24,000 usable gates 282 to 2,252 registers Fabricated on a 0.8-m icron CM OS SRAM technology


    OCR Scan     		PDF ALTED001 epf8282 hardware epf8282 block pf815 EPF81188 PF8150 EPF8282

    Untitled

    Abstract: No abstract text available
    Text: Advance Data Sheet February 1993 £ = — AT&T Microelectronics Optimized Reconfigurable Cell Array ORCA Series Field-Programmable Gate Arrays Features • High density: 3500 to 22,000 usable gates ■ High I/O: up to 288 usable I/O ■ High performance: 80 MHz system clock rate


    OCR Scan     		PDF 16-bit DS92-099FPGA

    Untitled

    Abstract: No abstract text available
    Text: FLEX 8000 Programmable Logic Device Family May 1999, ver. 10 Features. D a ta she et • ■ ■ ■ ■ Low-cost, high-density, register-rich CMOS programmable logic device PLD family (see Table 1) 2,500 to 16,000 usable gates 282 to 1,500 registers System-level features


    OCR Scan     		PDF EPF8452A EPF8636GC192 EPF8636A EPF8820A EPF81500A

    isplsi device layout

    Abstract: No abstract text available
    Text: Lattice ispLSr and pLSF 2064V \Semiconductor High Density Programmable Logic I Corporation Features Functional Block Diagram HIGH DENSITY PROGRAMMABLE LOGIC — — — — — 2000 PLD Gates 64 and 32 I/O Pin Versions, Four Dedicated Inputs 64 Registers High Speed Global Interconnect


    OCR Scan     		PDF 100MHz 064V-80LJ44 44-Pin 064V-80LT44 064V-60LJ84 84-Pin 064V-60LT100 100-Pin 064V-60LJ44 isplsi device layout

    Untitled

    Abstract: No abstract text available
    Text: Lattica ispLSr 2032V/LV I Semiconductor I Corporation 3.3V High Density Programmable Logic Functional Block Diagram Features HIGH DENSITY PROGRAMMABLE LOGIC — — — — — 1000 PLD Gates 32 I/O Pins, Two Dedicated Inputs 32 Registers High Speed Global Interconnect


    OCR Scan     		PDF 032V/LV 032V/LV 032V-100LJ44 44-Pin 032V-100LT44 2032LV-80LJ ispLSI2032LV-80LT44

    Untitled

    Abstract: No abstract text available
    Text: Lattice* ispLSr 2032V/LV ; ; ; Semiconductor •■■ Corporation 3.3V High Density Programmable Logic Features Functional Block Diagram • HIGH DENSITY PROGRAMMABLE LOGIC — — — — — 1000 PLD Gates 32 I/O Pins, Two Dedicated Inputs 32 Registers


    OCR Scan     		PDF 032V/LV 032V/LV 032V-100LJ44 44-Pin 032V-100LT44 2032LV-80LJ ispLSI2032LV-80LT44

    Untitled

    Abstract: No abstract text available
    Text: Lattica ispLSI 2032V I Semiconductor I Corporation 3.3V High Density Programmable Logic Functional Block Diagram Features HIGH DENSITY PROGRAMMABLE LOGIC — — — — — 1000 PLD Gates 32 I/O Pins, Two Dedicated Inputs 32 Registers High Speed Global Interconnect


    OCR Scan     		PDF 032V-100LJ44 44-Pin 032V-100LT44 032V-80LJ44 ispLSI2032V-80LT44 032V-60LJ44

    Untitled

    Abstract: No abstract text available
    Text: Lattice ; ; ; ; Semiconductor •• ■■ Corporation ispLSI 2032VL * VANTI S 2.5V In-System Programmable SuperFAST High Density PLD Functional Block Diagram Features SuperFAST HIGH DENSITY IN-SYSTEM PROGRAMMABLE LOGIC — — — — — 1000 PLD Gates


    OCR Scan     		PDF 2032VL 2032VE 44-Pin 2032VL-180LB49 49-Bail 2032VL-135LT44 2032VL-135LT48 48-Pin 2032VL-135LJ44