81110A
Abstract: 81130A CR2477 hz 91710 E8311A E8312A EN50082-1 IEC1010 811xx-91021 81104A
Text: Agilent 81100 Family of Pulse Pattern Generators Data Sheet – Version 1.3 Agilent 81110A Signals for testing digital designs and components Flexible Pulses or Patterns for Digital Designs – Key Features The Agilent 81101A, 81104A, 81110A and 81130A generate all
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1110A
1101A,
1104A,
1110A
1130A
5980-1215E
81110A
81130A
CR2477
hz 91710
E8311A
E8312A
EN50082-1
IEC1010
811xx-91021
81104A
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PLL variable frequency generator
Abstract: QPro Virtex 4 Hi-Rel PLL 02A DS614 fpga 3 phase inverter DS6-14 MMCM
Text: Clock Generator DS614 April 19, 2010 Product Specification Introduction LogiCORE IP Facts Core Specifics The Clock Generator module provides clocks according to system wide clock requirements. Virtex -6/6CX, Spartan®-6, Spartan-3A/3A DSP, Spartan-3, Spartan-3E, Automotive
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DS614
PLL variable frequency generator
QPro Virtex 4 Hi-Rel
PLL 02A
fpga 3 phase inverter
DS6-14
MMCM
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Untitled
Abstract: No abstract text available
Text: TOSHIBA TA8749S TO SH IBA BIPO LAR LINEAR IN TEGRATED CIRCUIT SILICON M ONOLITHIC TA8749S 4 fsc CLOCK GENERATOR The TA8749S provides the function for CCD clock driver, and generate 4 times frequency signal of the input fsc signal by PLL Circuit. FEATURES • 4 f sc VCO
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TA8749S
TA8749S
961001EBA2
58MHz,
98TYP
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CY22150
Abstract: CY22150F CY22150FC CY22150FI CY3672 CY3672ADP000
Text: CY22150 One-PLL General-Purpose Flash-Programmable and 2-Wire Serially Programmable Clock Generator Features Benefits • Integrated phase-locked loop PLL Internal PLL to generate six outputs up to 200 MHz. Able to generate custom frequencies from an external crystal or a driven source.
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CY22150
12H/D5
CY22150
CY22150F
CY22150FC
CY22150FI
CY3672
CY3672ADP000
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Function Generator 74hc4046 sine square triangle
Abstract: Function Generator IC sine square triangle Frequency Generator 0.1Hz 10MHz 74HC4046 0.1Hz 10MHz 74hc4046 PIN DIAGRAM 74HC4046 application note IC Generator to 2MHz square precision Sine Wave Generator variable frequency drive circuit diagram 74HC4046
Text: SIGNAL GENERATION CIRCUITS Application Note 650: Mar 13, 2000 Versatile Waveform Generator Operates from 0.1Hz to 20MHz As a single-chip source of high-frequency waveforms, the MAX038 can serve both as the core of a moderate-performance waveform generator, and as a card-level waveform source for electronic systems in
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20MHz
MAX038
20MHz.
50MHz,
16MHz
com/an650
Function Generator 74hc4046 sine square triangle
Function Generator IC sine square triangle
Frequency Generator 0.1Hz 10MHz
74HC4046 0.1Hz 10MHz
74hc4046 PIN DIAGRAM
74HC4046 application note
IC Generator to 2MHz square
precision Sine Wave Generator
variable frequency drive circuit diagram
74HC4046
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HMC939
Abstract: hmc597 TRANSIMPEDANCE mmic laser HMCAD1101 HMC676LP3E
Text: OFF-THE-SHELF Analog, Digital & Mixed-Signal ICs, Modules, Subsystems & Instrumentation New 10 MHz to 20 GHz Signal Generator! See Page 3 49 New Featured Products! 2W & 4W Power Amplifiers January 2011 Hittite Acquires Arctic Silicon Devices! New High Speed ADC Product Line
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NL-0111
HMC939
hmc597
TRANSIMPEDANCE mmic laser
HMCAD1101
HMC676LP3E
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CY22150
Abstract: CY22150FC CY22150FCT CY22150FI CY22150FZXC CY22150FZXCT CY22150FZXI CY3672 CY3672ADP000 CY22150FZ
Text: CY22150 One-PLL General-Purpose Flash-Programmable and 2-Wire Serially Programmable Clock Generator Features times, reducing inventory of custom parts and providing an easy method for upgrading existing designs. • Integrated phase-locked loop PLL • The CY22150 can be programmed at the package level.
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CY22150
CY22150
CY3672
12H/D5
CY22150FC
CY22150FCT
CY22150FI
CY22150FZXC
CY22150FZXCT
CY22150FZXI
CY3672ADP000
CY22150FZ
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Untitled
Abstract: No abstract text available
Text: CY22801 Universal Programmable Clock Generator UPCG Features General Description • Integrated phase-locked loop (PLL) ■ Field-programmable ■ Input frequency range: ❐ Crystal: 8 MHz to 30 MHz ❐ CLKIN: 1 MHz to 133 MHz The CY22801 is a flash-programmable clock generator that
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CY22801
CY22801
CY36800,
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AD9136
Abstract: ad9135
Text: FEATURES TYPICAL APPLICATION CIRCUIT Support input data rate >2 GSPS Proprietary low spurious and distortion design SFDR = 82 dBc at dc IF, −9 dBFS Flexible 8-lane JESD204B interface Multiple chip synchronization Fixed latency Data generator latency compensation
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JESD204B
88-lead
ADRF6720
JESD204B
AD9136
ad9135
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SIWARD 25 MHZ crystal
Abstract: SZ08
Text: CY22801 Universal Programmable Clock Generator UPCG Universal Programmable Clock Generator (UPCG) Features General Description • Integrated phase-locked loop (PLL) ■ Field-Programmable ■ Input frequency range: ❐ Crystal: 8 MHz to 30 MHz ❐ CLKIN: 1 MHz to 133 MHz
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CY22801
CY22801
CY36800,
SIWARD 25 MHZ crystal
SZ08
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DCM03
Abstract: vhdl code for All Digital PLL vhdl code for DCM vhdl code for phase shift Digital clock MODULE CIRCUIT DIAGRAM dcmi digital clock digital clock vhdl code CLK180 DS614
Text: Clock Generator DS614 June 24, 2009 Product Specification Introduction LogiCORE Facts The Clock Generator module provides clocks according to system wide clock requirements. Features • Automatic instantiation of Digital Clock Manager DCM modules and their connections
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DS614
DCM03
vhdl code for All Digital PLL
vhdl code for DCM
vhdl code for phase shift
Digital clock MODULE CIRCUIT DIAGRAM
dcmi
digital clock
digital clock vhdl code
CLK180
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Untitled
Abstract: No abstract text available
Text: CY22801 Universal Programmable Clock Generator UPCG Universal Programmable Clock Generator (UPCG) Features General Description • Integrated phase-locked loop (PLL) ■ Field-Programmable ■ Input frequency range: ❐ Crystal: 8 MHz to 30 MHz ❐ CLKIN: 1 MHz to 133 MHz
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CY22801
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sw60
Abstract: CXA1854AR LCX005 LCX005BK LCX009AK VR12 HSW175 VCO circuit diagram
Text: CXA1854AR Decoder/Driver/Timing Generator for Color LCD Panels For the availability of this product, please contact the sales office. Description The CXA1854AR is an IC designed exclusively to drive color LCD panels LCX009AK/AKB/LCX005BK/ BKB. This IC greatly reduces the number of circuits
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CXA1854AR
CXA1854AR
LCX009AK/AKB/LCX005BK/
LCX009AK/AKB/LCX005BK/BKB
LCX009
64PIN
LQFP-64P-L061
LQFP064-P-1010-AY
sw60
LCX005
LCX005BK
LCX009AK
VR12
HSW175
VCO circuit diagram
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Untitled
Abstract: No abstract text available
Text: SONY CXA1854AR Decoder/Driver/Timing Generator for Color LCD Panels Description The CXA1854AR is an IC designed exclusively to drive color LCD panels LCX009AK/AKB/LCX005BK/ BKB. This IC greatly reduces the number of circuits and parts required to drive LCD panels by
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CXA1854AR
CXA1854AR
LCX009AK/AKB/LCX005BK/
LCX009AK/AKB/LCX005BK/BKB
64PIN
FP-64P-L061
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exs00a
Abstract: EXS00A CRYSTAL BU3081FV Nihon Dempa Kogyo vco 27MHz exs00a ndk PLL VCO 27MHz Nihon Dempa Kogyo Co., Ltd 27mhz toys AF-S2
Text: BU3081FV Multimedia ICs Clock generator with built-in VCO, VCXO BU3081FV BU3081FV is a clock generator. It can generate four video / audio clock signals that is used for DVD recorder Especially for DVD recorder with DV interface of IEEE1394 from one reference frequency. Reference frequency suited for set
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BU3081FV
BU3081FV
IEEE1394)
SSOP-B28
exs00a
EXS00A CRYSTAL
Nihon Dempa Kogyo
vco 27MHz
exs00a ndk
PLL VCO 27MHz
Nihon Dempa Kogyo Co., Ltd
27mhz toys
AF-S2
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resistor bank
Abstract: No abstract text available
Text: SLG2209 3.3V High Performance Zero Delay Buffer 9 Outputs Output Summary Features • Part of Silego’s Media Timing Generator (MTG) Family • 2 - Banks of 4 Single-Ended Clock Outputs @ 3.3V • 3.3V Supply Operation • 1 - Single-Ended Clock Output @3.3V
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SLG2209
120ps
16-Pin
SLG2209H
resistor bank
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resistor bank
Abstract: SILEGO
Text: SLG2409 3.3V High Performance Zero Delay Buffer 9 Outputs Output Summary Features • Part of Silego’s Media Timing Generator (MTG) Family • 2 - Banks of 4 Single-Ended Clock Outputs @ 3.3V • 3.3V Supply Operation • 1 - Single-Ended Clock Output @3.3V
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SLG2409
250ps
200ps
16-Pin
SLG2409G
SLG2409GTR
SLG2409HG
resistor bank
SILEGO
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phase detector and up down counter
Abstract: phase detector
Text: Phase Locked Loops PLL in High-Speed Designs to generate the desired output frequency. Figure 1 is a block diagram of a simple PLL circuit. Introduction This application note describes the construction of a Phase Detector (PD) in conjunction with a Voltage Controlled Oscillator (VCO) to create a frequency generator
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phase detector
Abstract: digital phase detector Phase detectors application note phase detector and up down counter frequency generator single phase ups block diagram single phase ups circuit diagram an8017
Text: Phase Locked Loops PLL in High Speed Designs to generate the desired output frequency. Figure 1 is a block diagram of a simple PLL circuit. Introduction This application note describes the construction of a Phase Detector (PD) in conjunction with a Voltage Controlled Oscillator (VCO) to create a frequency generator
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CXA2543R
Abstract: DCX501BK LCX018AK SW62 SW64 SW59 DCX501
Text: CXA2543R Decoder/Driver/Timing Generator for Color LCD Panels For the availability of this product, please contact the sales office. Description The CXA2543R is an IC designed exclusively to drive the color LCD panel DCX501BK and LCX018AK. This IC greatly reduces the number of circuits and
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CXA2543R
CXA2543R
DCX501BK
LCX018AK.
LCX018AK
64PIN
LQFP-64P-L061
LQFP064-P-1010-AY
SW62
SW64
SW59
DCX501
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Silego Technology
Abstract: No abstract text available
Text: SLG2204 3.3V High Performance Zero Delay Buffer 4 Outputs Features Output Summary • Part of Silego’s Media Timing Generator (MTG) Family • 3.3V Supply Operation • 4 Output Zero Delay Buffer • External Feedback Input • Frequency Range: 10 to 200 MHz
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SLG2204
100ps
SLG2204
Silego Technology
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EP1S60
Abstract: "Single-Port RAM"
Text: Chapter 1. Introduction S51001-3.1 Introduction The Stratix family of FPGAs is based on a 1.5-V, 0.13-µm, all-layer copper SRAM process, with densities of up to 79,040 logic elements LEs and up to 7.5 Mbits of RAM. Stratix devices offer up to 22 digital signal
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S51001-3
420-MHz
EP1S60
"Single-Port RAM"
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vhdl code for complex multiplication and addition
Abstract: verilog code for 7-3 compressor vhdl code for 9 bit parity generator vhdl code for half adder logic diagram to setup adder and subtractor vhdl code for ROM multiplier A123 C789 M20K verilog code for 7-3 compressor in multiplier
Text: Section I. Device Core This section describes the Stratix V device family core, which is the most architecturally advanced, high-performance, low-power FPGA in the market place. This section includes the following chapters: • Chapter 1, Logic Array Blocks and Adaptive Logic Modules in Stratix V Devices
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FMD1216ME
Abstract: Philips TV tuners module td1316 fmd1216 tda10046 FQ1236 FQ1216ME FM1216ME tuv1236d Philips mk5
Text: RF SOLUTIONS PRODUCT OVERVIEW Multimedia Front-Ends Network Interface Modules Digital/Analog Terrestrial Tuners Digital/Analog Cable Tuners RF Input Modules Digital Satellite Tuners Mainstream TV Tuner FMD1216ME FQ1200 MK5 Hybrid DVB-T/Analog multistandard
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FMD1216ME
FQ1200
FMD1216ME
Philips TV tuners module
td1316
fmd1216
tda10046
FQ1236
FQ1216ME
FM1216ME
tuv1236d
Philips mk5
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