jat52

Abstract: TA-TSY-000191 PM5319 PM5319-NI PMC-2030860
Contextual Info: us t, 20 04 09 :2 1: 24 PM ARROW 622 ASSP Telecom Standard Product Data Sheet Released es da y, 10 Au g PM5319 gi es , In c. on Tu ARROW 622 Released Issue No. 2: July 2004 Do wn lo ad ed by Sc o tt E st es of i 2T ec h no lo ASSP Telecom Standard Product Data Sheet

Diode LT 228d

Abstract: 1E2H SMD making code DV5
Contextual Info: 7: 43 AM PM4323 OCTLIU LT Device ASSP Telecom Standard Product Data Sheet Released ,0 ay co n Th ur sd OCTLIU LT 1M ay ,2 00 8 01 :0 PM4323 of Pa rtm in er In Device Telecom Standard Product Proprietary and Confidential Released Issue No. 5: April 2008 Do

R4000

Abstract: RM5200 RM5261A
Contextual Info: RM5261A Microprocessor with 64-Bit System Bus Data Sheet Preliminary RM5261A™ RM5261A™ Microprocessor with 64-Bit System Bus Data Sheet Proprietary and Confidential Preliminary Issue 1, March 2001 Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use

R4000

Abstract: RM5200 RM5261A
Contextual Info: RM5261A Microprocessor with 64-Bit System Bus Data Sheet Preliminary RM5261A™ RM5261A™ Microprocessor with 64-Bit System Bus Data Sheet Proprietary and Confidential Preliminary Issue 2, September 2001 Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use

MIPS64

Abstract: RM9220
Contextual Info: RM9220 Released 54 4: :3 05 04 • Supports 25.6 Gbps memory. • Supports DDR SDRAM options. • Supports 2 Gbytes using 512 Mbit SDRAM and 4 Gbytes using 1 Gbit SDRAM. ADDITIONAL FEATURES • Provides 8 Kbytes integrated low latency scratch RAM. • Provides an integrated on-chip EJTAG

paladin 172 410

Contextual Info: 09 :3 1: 26 PM S/UNI IMA 4 Telecom Standard Product Data Sheet Released ,2 7M ar ch ,2 00 8 PM7348 In co n Th ur sd ay S/UNI IMA 4 Datasheet Proprietary and Confidential Released Issue No. 3: March 2008 Do wn lo ad ed [c on tro lle d] by Co nt en tT ea m of

Contextual Info: PM5376 TSE-Nx160 Released Transmission Switch Element FEATURES • Provides two pages of connection memory with software and hardware controlled hitless page swaps at frame boundaries. • Supports trunk conditioning on a per port, per egress grain basis for AIS and

32A1024

Contextual Info: PM7386 FREEDM 32A1024 Frame Engine and Datalink Manager FEATURES • Single-chip multi-channel packet processor supporting a maximum aggregate bandwidth of 64 Mbit/s for line rate throughput transfers of packet sizes from 40 to 9.6 Kbytes, for up to an aggregate of 32 T1s or 32 E1s.

RM9000

Contextual Info: CM5391L Preliminary GEN-M9K-20 Data Sheet 19 Flexible Clock Generators for MIPS 9K Based Systems AM A MEMBER OF THE PMC CLK FAMILY • 02 :2 7: PMC-Sierra’s CM5391L clock generator is the industry’s only device tailored to drive the clocking inputs of PMC-Sierra’s leading line of processors using MIPS 9K architectures, such as:

PM4329

Abstract: PMC-2021518 "TOPS" PQ-32/SBI-1
Contextual Info: 48 PM PM4329 HDLIU 32 Hardware Specification Released ch 6M ar nd ay ,2 HDLIU 32 ,2 00 6 10 :5 0: PM4329 rtm in er In co n Su Hardware Specification Released Do wn lo ad ed by Co nt e nt T ea m of Pa Issue No. 5: March 2006 Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.

Contextual Info: PM8354 QuadPHY 1G Preliminary 4-channel 1.0-1.25 Gbit/s Transceiver 25 :3 06 for the QuadPHY 1G. 03 PHYSICAL 20 • Ultra-low power operation using 0.18 µ CMOS technology. y, • Thermally enhanced, 289-pin, 19 mm x 19 mm CABGA package. • • • eb temperature range -40 to +85 °C and is

VOLTAGE DEPENDENT RESISTOR panasonic

Contextual Info: :2 5: 39 PM Octal Short-Haul E1/T1/J1 Line Interface Device Telecom Standard Product Data Sheet Released nd ay ,1 6S ep te OCTLIU-SH m be r, 20 07 10 PM4319 Data Sheet Proprietary and Confidential Released Issue No. 3: May 2002 Do wn l oa de d by I HS Pa r

SMD codes

Abstract: 063310
Contextual Info: QuadPHY 10GX ASSP Telecom Standard Product Data Sheet Released PM8358 QuadPHY® 10GX 4 X 1.2 to 3.2 Gbit/s Quad, Fully Redundant, XAUI to XGMII, 10 Gigabit Ethernet / Fibre Channel Physical Layer Device Data Sheet Released Issue No. 5: April 2004 Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.

Contextual Info: S W I T CHING T HE S M A R T WAY Reed Switches SMD Reed Switches Reed Sensors Level Sensors Magnets Sensor Technology Welcome to PIC Our work is never done. Passion, respect, integrity and discipline are the four core values which drive us to sophisticated

Contextual Info: PM8352 OctalPHY 1G Advance 8-channel 1.0-1.25 Gbits/s Transceiver • Eight independent 1.0 to 1.25 Gbit/s • • AM :3 08 • Dual Data Rate DDR parallel interface • • 03 20 • Ultra-low power operation using 0.18 µ CMOS technology. • Thermally enhanced, 289-pin, 19 mm x

Contextual Info: Octal E1/T1/J1 Line Interface Device Telecom Standard Product Data Sheet Released PM4318 OCTLIU Octal E1/T1/J1 Line Interface Device Telecom Standard Product Data Sheet Proprietary and Confidential Released Issue No. 6: May 2002 Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.

Contextual Info: PM5369 TUPP 9953 Tributary Unit Payload Processor for 9953 Mbit/s 5: 49 AM Released Product Brief • Provides hardware based Message Assisted Protection Switching :1 Product Highlights • io fI Block Diagram • • 01 2 01 Low Order Processor LOPP Perf. Mon/

Contextual Info: 6: 07 AM ARROW 12xETEC ASSP Telecom Standard Product Data Sheet Released us t, 20 04 11 :1 PM5385 Tu es da y, 03 Au g ARROW 12xETEC Data Sheet Released Issue No. 4: April 2004 Do wn lo ad ed by Sa nj iv Sh ar m ao fR SB SY ST EM S on Twelve channel E3/T3/STS-1E EC-1

Contextual Info: Octal Short-Haul E1/T1/J1 Line Interface Device Telecom Standard Product Data Sheet Released PM4319 OCTLIU-SH Octal Short-Haul E1/T1/J1 Line Interface Device Data Sheet Proprietary and Confidential Released Issue No. 3: May 2002 Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.

Contextual Info: Standard Products MIP7365 64-Bit Superscaler Microprocessor January 11, 2007 FEATURES ❑ Upscreened PMC-Sierra RM7065C ❑ Military and Industrial Grades Available ❑ Dual issue symmetric superscalar microprocessor with instruction prefetch optimized for system level

PM5397

Abstract: GR-253-CORE STM-16 STS-48 TDAT31
Contextual Info: PM5360 S/UNI MULTI 48 Released Multi-rate SATURN User Network Interface for 1x2488, 4x622, and 4x155 LINE_IF TXD_P/N[1] Transmit 2488 Mbps Analog Circuitry TXD_P/N[4:2] Transmit 622 Mbps Analog Circuitry Transmit Section Trace Processor 4 Transmit Line Interface

GR-253-CORE

Abstract: PM5358 PM5379 PM5382 "network interface cards"
Contextual Info: PM5379 S/UNI 4x155 Release 4-Channel OC-3c ATM and POS Physical Layer Device FEATURES • Provides UTOPIA Level 3 compatible 32-bit wide System Interface clocked up to 104 MHz with parity support for ATM applications. • Provides SATURN POS-PHY Level 3 32-bit System Interface

SDH ADM

Abstract: PM5324 PM5326 PM5370 PM5377 PM5369 extended sonet serial interface
Contextual Info: PM5369 TUPP 9953 Preliminary Tributary Unit Payload Processor for 9953 Mbit/s FEATURES • Configurable, multi-channel payload processor for aligning SONET virtual tributaries VTs or SDH tributary units (TUs) in an STS-192/STM-64 or STS-48/STM-16 data stream.

PM8368

Abstract: PM8372
Contextual Info: PM8368 PBC-18x2G Preliminary 18-Port FC-AL Port Bypass Controller GENERAL • Supports 18 Fibre Channel Physical Interfaces at 1.0625 or 2.125 Gbit/s per Fibre Channel - Physical Interface FC-PI . • Each port independently selectable to perform a retimer, repeater or analog