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Catalog Datasheet	MFG & Type	Document Tags	PDF
00XXX001 Abstract: BA 5979 R15C3 OR3T125 OR3T20 OR3T30 OR3T55 PT10 PT11 PT12 Text: Data Sheet November 2006 ORCA Series 3C and 3T Field-Programmable Gate Arrays Features • ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ Baseline FPGA family used in Series 3+ FPSCs field programmable system chips which combine FPGA logic	Original	OR3T20 OR3T30 1A-06. OR3T80 00XXX001 BA 5979 R15C3 OR3T125 OR3T20 OR3T30 OR3T55 PT10 PT11 PT12	PDF
MachXO sysIO Usage Guide Abstract: LCMXO256C-4M100C LCMXO2280 lcmxo640c-3tn100i LCMXO640C-3FT256C LCMXO1200 LCMXO256 LCMXO2280E-4M132I LVCMOS15 LVCMOS25 Text: MachXO Family Data Sheet Version 02.3_4W February 2007 MachXO Family Data Sheet Introduction April 2006 Data Sheet • Flexible I/O Buffer Features • Programmable sysIO buffer supports wide range of interfaces: − LVCMOS 3.3/2.5/1.8/1.5/1.2 − LVTTL	Original	TN1086) TN1087) TN1097) MachXO sysIO Usage Guide LCMXO256C-4M100C LCMXO2280 lcmxo640c-3tn100i LCMXO640C-3FT256C LCMXO1200 LCMXO256 LCMXO2280E-4M132I LVCMOS15 LVCMOS25	PDF
TPE11 Abstract: TPT20 CON6A v2 tpr4 pr48b PT13B condor E5 Condor LVCMOS15 LVCMOS25 Text: LatticeEC Standard Evaluation Board – Revision B User’s Guide April 2007 ebug10_01.4 Lattice Semiconductor LatticeEC Standard Evaluation Board – Revision B User’s Guide Introduction The LatticeEC Standard Evaluation Board provides a convenient platform to evaluate, test and debug user	Original	ebug10 120-pin) 32-bit PVG5H503A01 TPE11 TPT20 CON6A v2 tpr4 pr48b PT13B condor E5 Condor LVCMOS15 LVCMOS25	PDF
OSC4/SM Abstract: MDLS-20265 OPTREX C-51505 MDLS-24265 short stop 12v p18 30a rs232 converter dmx Mosfet J49 LCM-S01602 lcm-s02402 Vishay SOT23 MARKING F5 Text: LatticeXP2 Advanced Evaluation Board User’s Guide January 2009 Revision: EB30_01.3 LatticeXP2 Advanced Evaluation Board User’s Guide Lattice Semiconductor Introduction The LatticeXP2 Advanced Evaluation Board provides a convenient platform to evaluate, test and debug user	Original	LatticeXP2-17 24-6R8 OSC4/SM MDLS-20265 OPTREX C-51505 MDLS-24265 short stop 12v p18 30a rs232 converter dmx Mosfet J49 LCM-S01602 lcm-s02402 Vishay SOT23 MARKING F5	PDF
CON6A Abstract: K4T51163QG-HCE60 pDS4102-DL2 LVCMOS33 LVCMOS15 LVCMOS25 PB50B TPE11 PL43A FPGA48 Text: LatticeEC Standard Evaluation Board – Revision A User’s Guide April 2007 EB07_02.4 Lattice Semiconductor LatticeEC Standard Evaluation Board – Revision A User’s Guide Introduction The LatticeEC Standard Evaluation Board provides a convenient platform to evaluate, test and debug user	Original	120-pin) 32-bit PVG5H503A01 CON6A K4T51163QG-HCE60 pDS4102-DL2 LVCMOS33 LVCMOS15 LVCMOS25 PB50B TPE11 PL43A FPGA48	PDF
LC4064ZE Abstract: BSDL Files infineon LFXP6C-3FN256I "x-ray machine" K4H560838E LC4064 LC4256ZE LFXP10C-3F256I LFxP3C-3TN144C PCI x1 express PCB dimensions artwork Text: LatticeXP Family Handbook HB1001 Version 03.4, September 2010 LatticeXP Family Handbook Table of Contents September 2010 Section I. LatticeXP Family Data Sheet Introduction Features . 1-1	Original	HB1001 TN1050 TN1049 TN1082 TN1074 LC4064ZE BSDL Files infineon LFXP6C-3FN256I "x-ray machine" K4H560838E LC4064 LC4256ZE LFXP10C-3F256I LFxP3C-3TN144C PCI x1 express PCB dimensions artwork	PDF
syscon Abstract: LFEC1E-3T100C ips works 6CW3 Text: LatticeECP/EC Family Data Sheet Version 01.3 LatticeECP/EC Family Data Sheet Introduction November 2004 Preliminary Data Sheet Features − − − − − − • Extensive Density and Package Options • 1.5K to 41K LUT4s • 65 to 576 I/Os • Density migration supported	Original	36x36 18x18 DDR400 200MHz) TN1052) TN1057) TN1053) syscon LFEC1E-3T100C ips works 6CW3	PDF
Untitled Abstract: No abstract text available Text: LatticeXP Family Data Sheet Version 04.4, April 2006 LatticeXP Family Data Sheet Introduction December 2005 Data Sheet • Flexible I/O Buffer Features • Programmable sysIO buffer supports wide range of interfaces: − LVCMOS 3.3/2.5/1.8/1.5/1.2 − LVTTL	Original	HSTL15 TN1050) TN1052) TN1082)	PDF
Untitled Abstract: No abstract text available Text: LatticeXP Family Data Sheet Version 03.0, September 2005 LatticeXP Family Data Sheet Introduction July 2005 Advance Data Sheet • Flexible I/O Buffer Features • Programmable sysIO buffer supports wide range of interfaces: − LVCMOS 3.3/2.5/1.8/1.5/1.2	Original	HSTL15 TN1050) TN1052) TN1082)	PDF
pt45 Abstract: No abstract text available Text: LatticeSC Family Data Sheet DS1004 Version 01.2, June 2006 LatticeSC Family Data Sheet Introduction June 2006 Preliminary Data Sheet DS1004 Features • High Performance FPGA Fabric • 15K to 115K four input Look-up Tables LUT4s • 132 to 942 I/Os • 700MHz global clock; 1GHz edge clocks	Original	DS1004 DS1004 700MHz 600Mbps 125Gbps) 110mW VCC12. LFSC25 900-Ball pt45	PDF
Untitled Abstract: No abstract text available Text: LatticeECP/EC Family Handbook HB1000 Version 03.7, September 2012 LatticeECP/EC Family Handbook Table of Contents September 2012 Section I. LatticeECP/EC Family Data Sheet Introduction Features . 1-1	Original	HB1000 TN1008 TN1010 TN1018 TN1071 TN1074 TN1078	PDF
IC TTL 7495 diagram and truth table Abstract: BA 5979 S AM 5766 BA 5979 motorola s240 pin diagram of ic 7495 Xilinx counter transistor on 4409 PR25D inverter design using plc Text: Data Sheet June 1999 ORCA Series 3C and 3T Field-Programmable Gate Arrays Features • ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ High-performance, cost-effective, 0.35 µm OR3C and 0.3 µm (OR3T) 4-level metal technology, (4- or 5-input look-up table delay of 1.1 ns with -7 speed grade in	Original	DS99-087FPGA DS98-163FPGA-01) IC TTL 7495 diagram and truth table BA 5979 S AM 5766 BA 5979 motorola s240 pin diagram of ic 7495 Xilinx counter transistor on 4409 PR25D inverter design using plc	PDF
PT35c transistor Abstract: pt35c transistor pt36c me 4946 PBGA PR25D transistor on 4409 307-45 4946 ah lm 458 ic Text: Data Addendum March 2002 ORCA OR3LxxxB Series Field-Programmable Gate Arrays Introduction This data addendum refers to the information found in the ORCA® Series 3C and 3T Field-Programmable Gate Arrays Data Sheet. • ■ Features ■ ■ ■ ■ ■ ■	Original	16-bit OR3L165B OR3L225B OR3L165B7PS208I-DB OR3L165B7PS240I-DB OR3L165B7BA352I-DB OR3L165B7BC432I-DB OR3L165B7BM680I-DB OR3L225B7BC432I-DB OR3L225B7BM680I-DB PT35c transistor pt35c transistor pt36c me 4946 PBGA PR25D transistor on 4409 307-45 4946 ah lm 458 ic	PDF
transistor pt36c Abstract: datasheet transistor pt36C PT35c transistor pt36c microprocessor block diagram of plc pt35c transistor pt42c PT42C transistor BC 157 PLC Communication cables pin diagram Text: Data Sheet November, 2003 ORCA Series 4 FPGAs Introduction • Traditional I/O selections: — LVTTL 3.3V and LVCMOS (2.5 V and 1.8 V) I/Os. — Per pin-selectable I/O clamping diodes provide 3.3 V PCI compliance. — Individually programmable drive capability:	Original	sink/12 transistor pt36c datasheet transistor pt36C PT35c transistor pt36c microprocessor block diagram of plc pt35c transistor pt42c PT42C transistor BC 157 PLC Communication cables pin diagram	PDF

BA 5979 S Abstract: or3t806ba352-db 2764 EEPROM BA 5979 BL06 transistor OR3T125 OR3T20 OR3T30 OR3T55 PT10 Text: Data Sheet November 2006 ORCA Series 3C and 3T Field-Programmable Gate Arrays Features • ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ High-performance, cost-effective, 0.35 m OR3C and 0.3 μm (OR3T) 4-level metal technology, (4- or 5-input look-up table delay of 1.1 ns with -7 speed grade in	Original	OR3C804PS208I-DB OR3C804BA352I-DB OR3T206S208I-DB OR3T306S208I-DB OR3T306S240I-DB OR3T306BA256I-DB OR3T556PS208I-DB1 OR3T556S208I-DB OR3T556PS240I-DB OR3T556BA256I-DB BA 5979 S or3t806ba352-db 2764 EEPROM BA 5979 BL06 transistor OR3T125 OR3T20 OR3T30 OR3T55 PT10	PDF
Untitled Abstract: No abstract text available Text: LatticeSC/M Family Data Sheet DS1004 Version 02.1, June 2008 LatticeSC/M Family Data Sheet Introduction January 2008 Data Sheet DS1004 Features • High Performance FPGA Fabric • 15K to 115K four input Look-up Tables LUT4s • 139 to 942 I/Os • 700MHz global clock; 1GHz edge clocks	Original	DS1004 DS1004 700MHz 600Mbps 125Gbps) 105mW	PDF
Untitled Abstract: No abstract text available Text: MachXO Family Handbook HB1002 Version 02.0, November 2007 MachXO Family Handbook Table of Contents November 2007 Section I. MachXO Family Data Sheet Introduction Features . 1-1	Original	HB1002 TN1086 TN1090 TN1091 TN1092	PDF
Lattice Semiconductor Package Diagrams 256-Ball fpBGA Abstract: 16-bit adder Text: LatticeECP2/M Family Data Sheet DS1007 Version 02.1, September 2006 LatticeECP2/M Family Data Sheet Introduction September 2006 Advance Data Sheet DS1007 • Pre-Engineered Source Synchronous I/O Features • DDR registers in I/O cells • Dedicated gearing logic	Original	DS1007 DS1007 200MHz) ECP2-12. Lattice Semiconductor Package Diagrams 256-Ball fpBGA 16-bit adder	PDF
BGA 927 Abstract: No abstract text available Text: MachXO Family Handbook HB1002 Version 01.9, February 2007 MachXO Family Handbook Table of Contents February 2007 Section I. MachXO Family Data Sheet Introduction Features . 1-1	Original	HB1002 TN1089 TN1092 BGA 927	PDF
Untitled Abstract: No abstract text available Text: LatticeSC Family Data Sheet Version 01.1, April 2006 LatticeSC Family Data Sheet Introduction April 2006 Preliminary Data Sheet Features • High Performance FPGA Fabric • 15K to 115K four input Look-up Tables LUT4s • 132 to 942 I/Os • 700MHz global clock; 1GHz edge clocks	Original	700MHz 622Mbps 125Gbps) 100mW TN1101)	PDF
prbs pattern generator using vhdl Abstract: BUT16 Text: LatticeECP2/M Family Handbook HB1003 Version 04.9, April 2011 LatticeECP2/M Family Handbook Table of Contents April 2011 Section I. LatticeECP2/M Family Data Sheet Introduction Features . 1-1	Original	HB1003 TN1113 TN1149 TN1102 TN1103 TN1105 TN1107 TN1108 TN1109 TN1124 prbs pattern generator using vhdl BUT16	PDF
LFEC6E-3T144C Abstract: PT15B EC656 Text: LatticeECP/EC Family Data Sheet Version 02.2, March 2006 LatticeECP/EC Family Data Sheet Introduction May 2005 Data Sheet Features − − − − − − • Extensive Density and Package Options • 1.5K to 32.8K LUT4s • 65 to 496 I/Os • Density migration supported	Original	36x36 18x18 DDR400 200MHz) SSTL18 HSTL15 TN1052) TN1057) TN1053) LFEC6E-3T144C PT15B EC656	PDF
lfe2 Abstract: PL25B Text: LatticeECP2/M Family Data Sheet DS1006 Version 02.6, April 2007 LatticeECP2/M Family Data Sheet Introduction April 2007 Advance Data Sheet DS1006 • Pre-Engineered Source Synchronous I/O Features • DDR registers in I/O cells • Dedicated gearing logic	Original	DS1006 DS1006 200MHz) 266MHz) 256fpBGA 484-fpBGA ECP2M35E. 266MHz. 1152-fpBGA ECP2M70 lfe2 PL25B	PDF
Untitled Abstract: No abstract text available Text: AT&T Data Sheet October 1995 Microelectronics Optimized Reconfigurable Cell Array ORCA 2C Series Field-Programmable Gate Arrays Features Description • High-performance, cost-effective 0.5 \|im technology (four-input look-up table delay less than 3.6 ns)	OCR Scan	ATT2C04, ATT2C06, ATT2C08, ATT2C10, ATT2C12, ATT2C15, ATT2C26, ATT2C40. DS95-183FPGA DS95-031	PDF

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PR17B Search Results

PR17B Datasheets Context Search

00XXX001

MachXO sysIO Usage Guide

TPE11

OSC4/SM

CON6A

LC4064ZE

syscon

Untitled

Untitled

pt45

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IC TTL 7495 diagram and truth table

PT35c transistor

transistor pt36c

BA 5979 S

Untitled

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Lattice Semiconductor Package Diagrams 256-Ball fpBGA

BGA 927

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prbs pattern generator using vhdl

LFEC6E-3T144C

lfe2

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