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    PROGRAMMABLE LOGIC ARRAY FEATURES Search Results

    PROGRAMMABLE LOGIC ARRAY FEATURES Result Highlights (5)

    Part ECAD Model Manufacturer Description Download Buy
    DFE2016CKA-1R0M=P2 Murata Manufacturing Co Ltd Fixed IND 1uH 1800mA NONAUTO Visit Murata Manufacturing Co Ltd
    BLM15PX121BH1D Murata Manufacturing Co Ltd FB SMD 0402inch 120ohm POWRTRN Visit Murata Manufacturing Co Ltd
    BLM15PX181SH1D Murata Manufacturing Co Ltd FB SMD 0402inch 180ohm POWRTRN Visit Murata Manufacturing Co Ltd
    MGN1S1208MC-R7 Murata Manufacturing Co Ltd DC-DC 1W SM 12-8V GAN Visit Murata Manufacturing Co Ltd
    LQW18CN55NJ0HD Murata Manufacturing Co Ltd Fixed IND 55nH 1500mA POWRTRN Visit Murata Manufacturing Co Ltd

    PROGRAMMABLE LOGIC ARRAY FEATURES Datasheets Context Search

    Catalog Datasheet Type Document Tags PDF

    DIN173

    Abstract: application of programmable array logic 20L10 PLUS173
    Text: Philips Semiconductors Programmable Logic Devices Product specification Programmable logic array 22 x 42 × 10 DESCRIPTION PLUS173–10 FEATURES The PLUS173–10 PLD is a high speed, combinatorial Programmable Logic Array. The Philips Semiconductors state-of-the-art


    Original     		PLUS173 24-pin DIN173 NIN173 DIN173 application of programmable array logic 20L10 PDF

    16l8 JEDEC fuse

    Abstract: DIN153 Programmable Logic Array PLUS153-10N PLUS153 16L8 PLUS153-10A
    Text: Philips Semiconductors Programmable Logic Devices Product specification Programmable logic array 18 x 42 × 10 DESCRIPTION PLUS153–10 FEATURES The PLUS153–10 PLD is a high speed, combinatorial Programmable Logic Array. The Philips Semiconductors state-of-the-art


    Original     		PLUS153 20-pin DIN153 NIN153 16l8 JEDEC fuse DIN153 Programmable Logic Array PLUS153-10N 16L8 PLUS153-10A PDF

    RCT5 rn

    Abstract: d-latch by using D flip-flop 7474 7474 counter circuit diagram I18N 8 bit barrel shifter
    Text: Philips Components-Signetics Designing with Programmable Macro Logic Program m able Logic Devices INTRODUCTION TO PML DESIGN CONCEPTS Programmable Macro Logic, an extension of the Programmable Logic Array PLA concept combines a programming or fuse array with


    OCR Scan     		PLHS501 RCT5 rn d-latch by using D flip-flop 7474 7474 counter circuit diagram I18N 8 bit barrel shifter PDF

    ic D flip flop 7474

    Abstract: IC 7474 truthtable philips for ic 7474 7474 D flip-flop circuit diagram PLHS502 7474 D flip-flop IC 7474 flipflop pin DIAGRAM OF IC 7474 INTERNAL DIAGRAM OF IC 7474 any boolean circuit using nand gates
    Text: Philips Semiconductors Programmable Logic Devices Designing with programmable macro logic INTRODUCTION TO PROGRAMMABLE MACRO LOGIC DESIGN CONCEPTS Programmable Macro Logic PML , an extension of the Programmable Logic Array (PLA) concept combines a programming or


    Original     		PLHS501 4-to-16 5-to-32 16-to-4 32-to-5 16-to-1 27-to-1 ic D flip flop 7474 IC 7474 truthtable philips for ic 7474 7474 D flip-flop circuit diagram PLHS502 7474 D flip-flop IC 7474 flipflop pin DIAGRAM OF IC 7474 INTERNAL DIAGRAM OF IC 7474 any boolean circuit using nand gates PDF

    PLS161

    Abstract: PLS161N
    Text: PLS161 Signetics Field-Programmable Logic Array 12 X 48 X 8 Signetics Programmable Logic Product Specification Application Specific Products • Series 24 DESCRIPTION FEATURES The PLS161 is a bipolar, Field-Programmable Logic Array (FPLA). The device utilizes the standard AND/OR/lnvert ar­


    OCR Scan     		PLS161 PLS161 PLS161N PDF

    XC2064

    Abstract: XC2000 XC2018
    Text:  XC2000 Logic Cell Array Family Product Specifications Features Description • Fully Field-Programmable: The Logic Cell Array LCA is a high density CMOS integrated circuit. Its user-programmable array architecture is made up of three types of configurable elements:


    Original     		XC2000 XC2064 XC2000 XC2018 PDF

    Untitled

    Abstract: No abstract text available
    Text: DENSE-PAC Programmable Logic DPL22V10A MICROSYSTEMS DESCRIPTION: The Dense-Pac Programmable Logic Module DPL is a 48-pin Pin Grid Array (PGA) designed to support two "22V10" field programmable array logic, 22 input, 10 macrocell output devices (DPL22V10A), including decoupling capacitors, at a


    OCR Scan     		DPL22V10A 48-pin 22V10" DPL22V10A) DPL22V1 24-pin 28-pad 22V10 L22V10 PDF

    Untitled

    Abstract: No abstract text available
    Text: INTERNATIONAL CMOS TECHNOLOGY, INC. Preliminary Data TM PA7024 PEEL Array CMOS Programmable Electrically Erasable Logic Array Features User-Configurable High Density Logic Array — — — — Flexible Architecture Create multi-level l/O-buried logic circuits


    OCR Scan     		PA7024 100mA PDF

    Untitled

    Abstract: No abstract text available
    Text: INTERNATIONAL CMOS TECHNOLOGY, INC. Preliminary Data TM PA7040 PEEL Array CMOS Programmable Electrically Erasable Logic Array Features Flexible Architecture User-Configurable High Density Logic Array — — — — Create multi-level l/O-buried logic circuits


    OCR Scan     		PA7040 120mA PDF

    PA7140J-20

    Abstract: PA7140P-25 LCC14 PA7140 PA7140F-20 PA7140JN-20 PA7140P-20 "Programmable Electrically Erasable Logic Array"
    Text: Commercial/ Industrial PA7140 PEELTM Array Features • ■ Programmable Electrically Erasable Logic Array Versatile Logic Array Architecture - 24 I/Os, 14 inputs, 60 registers/latches - Up to 72 logic cell output functions - PLA structure with true product-term sharing


    Original     		PA7140 13ns/20ns 40-pin 44-pin PA7140P-20 PA7140F-20 13/20ns PA7140J-20 PA7140JN-20 PA7140P-25 PA7140J-20 PA7140P-25 LCC14 PA7140F-20 PA7140JN-20 PA7140P-20 "Programmable Electrically Erasable Logic Array" PDF

    "XOR Gate"

    Abstract: karnaugh map 8 pin dip j k flipflop ic
    Text: PAL22RX8A High Speed Programmable Array Logic Ordering Inform ation Features/ Benefits • Programmable flip-flops allow J-K, S-R, T or D-types for the most efficient use of product terms PAL22RX8A C NS STD PROGRAMMABLE ARRAY LOGIC • 8 Input/output macrocells for flexibility


    OCR Scan     		24-pin 300-mil 28-pin PAL22RX8A PAL22RX8A "XOR Gate" karnaugh map 8 pin dip j k flipflop ic PDF

    22V10PLD

    Abstract: 74ls74 timing setup hold PA7Q24
    Text: PA7024 PEEL Array mimi SEMICONDUCTORS February 1993 Features General Description User-Configurable High Density Logic Array The PA7024 is a user-configurable high-density Programmable Electrically Erasable Logic PEEL Array for creating multi-level, l/O-buried, logic circuits. Designed


    OCR Scan     		PA7024 24-pin 28-pin 22V10PLD 74ls74 timing setup hold PA7Q24 PDF

    FLEX 9000 family

    Abstract: No abstract text available
    Text: FLEX 10K Embedded-Array Programmable Logic Device Family March 1995, ver. 1 Features Preliminary Information Advance Information Brief • ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ High-density, embedded-array programmable logic device family


    OCR Scan     		EPF10K10 EPF10K20 EPF10K30 EPF10K40 EPF10K50 EPF10K70 EPF10K100 FLEX 9000 family PDF

    Untitled

    Abstract: No abstract text available
    Text: Preliminary Information INC. TM PA7128 PEEL Array CMOS Programmable Electrically Erasable Logic Array Features Flexible Architecture User-Configurable High Density Logic Array — — — — — — Create multi-level l/O-buried logic circuits O ver 50 sum -of-products functions


    OCR Scan     		PA7128 PDF

    Untitled

    Abstract: No abstract text available
    Text: PA7140 INC. PA7140 PEEL Array Programmable Electrically Erasable Logic Array Features • Versatile Logic Array Architecture - ■ ■ 24 l/Os, 14 inputs, 60 registers/latches Up to 72 logic cell output functions PLA structure w ith true product-term sharing


    OCR Scan     		PA7140 PA7140 40-pin 44-pin As7/25ns 17/25ns PA7140JI-25 PA7140JN-25 PDF

    Untitled

    Abstract: No abstract text available
    Text: Military CMOS Programmable Gate Array Logic Cell Array M 2 0 6 4 /M 2 0 1 8 Conforms to MIL-STD-883, Class B* Ordering Information Benefits Features CMOS • Low power • TTL or CMOS Input threshold levels PROGRAMABLE • Programmable Logic unctions • Programmable I/O blocks


    OCR Scan     		MIL-STD-883, M2018 M2064 M2018 A0-A15 PDF

    LCA-MEK01

    Abstract: 2064 ram
    Text: Military CMOS Programmable Gate Array Logic Cell Array M 2064/M 2018 Conforms to MIL-STD-883, Class B* Ordering Information Benefits Features CM OS • Low power • T T L or CM OS input threshold levels PROGRAM ABLE • Programmable Logic functions • Programmable I/O blocks


    OCR Scan     		2064/M MIL-STD-883, M2018 M2064 M2018 -55CC -125aC A0-A15 LCA-MEK01 2064 ram PDF

    PML2552-50A

    Abstract: EST 7502 C DIN552 est 7502
    Text: Philips Semiconductors Programmable Logic Devices Product specification CMOS high density programmable macro logic FEATURES DESCRIPTION • Full connectivity The Philips Semiconductors PML family of PLDs provides "instant gate array" capabilities for general purpose logic


    OCR Scan     		PML2552 630mW 525mW 15Wsec/cm2. 000jiW/cm2 7258Wsec/cm* PML2552-50A EST 7502 C DIN552 est 7502 PDF

    PAL10L8

    Abstract: PAL14L4 pal16l2 PAL10L8 logic diagram PAL10L8A PAL12L6
    Text: National Semiconductor Programmable Array Logic PAL 20-Pin Small PAL Family General Description The Small PAL logic array has between 10 and 16 comple­ mentary Input pairs and up to 8 combinatorial outputs gener­ ated by a single programmable AND-gate array with fixed


    OCR Scan     		20-Pin PAL14L4 PAL16L2 PAL10L8 PAL14L4 pal16l2 PAL10L8 logic diagram PAL10L8A PAL12L6 PDF

    THX 201

    Abstract: 26V12 PA7536 I326
    Text: PA7536 PEEL Array Programmable Electrically Erasable Logic Array Versatile Logic Array Architecture - 12 I/Os, 14 inputs, 36 registers/latches - Up to 36 logic cell output functions - PLA structure with true product-term sharing - Logic functions and registers can be I/O-buried


    Original     		PA7536 28-pin 4-02-052A THX 201 26V12 I326 PDF

    pal macrocells

    Abstract: No abstract text available
    Text: MAPL244 44-Pin Multiple Array Programmable Logic General Description Features The MAPL244 is a medium density, electrically erasable CMOS EECMOS programmable logic device based on a proprietary National Semiconductor programmable logic ar­ ray architecture. The MAPL244 integrates paged Field Pro­


    OCR Scan     		MAPL244 44-Pin 13ttn Cep-01451, pal macrocells PDF

    28U1

    Abstract: 22V10
    Text: DENSE-PAC MICROSYSTEMS Programmable Logic DPL22V10A D ESC R IP TIO N : The Dense-Pac Programmable Logic Module DPL ¡s a 48-p¡n Pin Grid Array (PGA) designed to support two "2 2 V 1 0 " field programmable array logic, 22 input, 10 macrocell output devices (D PL22V10A), including decoupling capacitors, at a


    OCR Scan     		DPL22V10A 22V10" DPL22V10A) DPL22V1 24-pin 28-pad 22V10 L22V10 48-PIN 28U1 PDF

    EK-025-8902

    Abstract: No abstract text available
    Text: H D G p GDK] / EPL204ED/EP EK-025-8902 CMOS ELECTRICALLY PROGRAMMABLE LOGIC • OUTLINE The EPL204 is a field programmable logic array manufactured by using CMOS EPROM processes. It is a programmable "and" fixed " o r " array w ith registered outputs in the 26P8


    OCR Scan     		EPL204ED/EP EK-025-8902 EPL204 EPL204 DIP-20-G1) EK-025-8902 PDF

    PAL10P8

    Abstract: PAL10P8A
    Text: « . Kl* «*, Programmable Array Logic Family XZZSSgSL*. / / / / /////////////////////////////////////MDVANCE INFORMATION Features/ Benefits • 25 ns maximum propagation delay Product Description • Programmable output polarity PART N UM BER PKG • Programmable replacement lor TTL logic


    OCR Scan     		PAL10P8A PAL14P4A PAL16P2A PAL16C1A 10-input 12-input 14-input 16-input PAL10P8A PAL10P8 PDF