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    Phoenix Contact 2900392 (ALTERNATE: PLC-OPT- 36DC/110DC/3RW)

    Relay;solid state;36 VDC;DIN rail;1 N/O contact | Phoenix Contact 2900392
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    RS 2900392 (ALTERNATE: PLC-OPT- 36DC/110DC/3RW) Bulk 10
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    • 10 $62.59
    • 100 $59.46
    • 1000 $53.2
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    Phoenix Contact 2900392

    Solid State Relays - SSRs PLC-OPT- 36DC/ 110DC/3RW
    Distributors Part Package Stock Lead Time Min Order Qty Price Buy
    TTI 2900392 Each 10
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    • 10 $49.63
    • 100 $45.67
    • 1000 $43.9
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    Phoenix Contact PLC-OPT- 36DC/110DC/3RW

    PLC-INTERFACE for railway applications - consisting of basic terminal block with push-in connection and integrated miniature solid-state relay - range: 0.7 x U<sub>N</sub> to 1.25 x U<sub>N</sub> - temperature range: -25°C to +70°C - 1 N/O contact - input: 36 V DC - output: 12 - 140 V DC/3 A
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    Master Electronics PLC-OPT- 36DC/110DC/3RW 3
    • 1 $55.98
    • 10 $49.99
    • 100 $45.5
    • 1000 $44.82
    • 10000 $44.82
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    PT36D Datasheets Context Search

    Catalog Datasheet MFG & Type Document Tags PDF

    transistor pt36c

    Abstract: gp714 diode GP113 transistor pt42c diode gp116 GP114 GP021 PT36c gp627 GP111
    Text: OR4E FPGA Ver 2.0 1 4/1/2002 Lattice Semiconductor Corp Series 4 FPGA Evaluation Board Diagram Revision 2.0 OR4E FPGA Ver 2.0 2 4/1/2002 Lattice Semiconductor Corp JTAG Programming Connection J55 Schematic page 4 An 8-pin connection to the JTAG interface used for programming.


    Original     		ADDR17 ADDR16 DATA31 DATA30 DATA29 DATA28 DATA27 DATA26 DATA25 DATA24 transistor pt36c gp714 diode GP113 transistor pt42c diode gp116 GP114 GP021 PT36c gp627 GP111 PDF

    30021

    Abstract: L48C L41C IC L44C DATASHEET L30C l31c L43C ORSO42G5 ORSO82G5 ORT42G5
    Text: ORCA ORSO42G5 and ORSO82G5 0.6 - 2.7 Gbps SONET Backplane Interface FPSCs August 2005 Data Sheet Introduction Lattice has extended its family of high-speed serial backplane devices with the ORSO42G5 and ORSO82G5 devices. Built on the Series 4 reconfigurable embedded System-on-a-Chip SoC architecture, the ORSO42G5 and


    Original     		ORSO42G5 ORSO82G5 ORSO82G5 ORSO42G5-1BMN484I ORSO82G5-2FN680I 30021 L48C L41C IC L44C DATASHEET L30C l31c L43C ORT42G5 PDF

    pt45

    Abstract: No abstract text available
    Text: LatticeSC Family Data Sheet DS1004 Version 01.2, June 2006 LatticeSC Family Data Sheet Introduction June 2006 Preliminary Data Sheet DS1004 Features • High Performance FPGA Fabric • 15K to 115K four input Look-up Tables LUT4s • 132 to 942 I/Os • 700MHz global clock; 1GHz edge clocks


    Original     		DS1004 DS1004 700MHz 600Mbps 125Gbps) 110mW VCC12. LFSC25 900-Ball pt45 PDF

    PT35c transistor

    Abstract: pt35c transistor pt36c me 4946 PBGA PR25D transistor on 4409 307-45 4946 ah lm 458 ic
    Text: Data Addendum March 2002 ORCA OR3LxxxB Series Field-Programmable Gate Arrays Introduction This data addendum refers to the information found in the ORCA® Series 3C and 3T Field-Programmable Gate Arrays Data Sheet. • ■ Features ■ ■ ■ ■ ■ ■


    Original     		16-bit OR3L165B OR3L225B OR3L165B7PS208I-DB OR3L165B7PS240I-DB OR3L165B7BA352I-DB OR3L165B7BC432I-DB OR3L165B7BM680I-DB OR3L225B7BC432I-DB OR3L225B7BM680I-DB PT35c transistor pt35c transistor pt36c me 4946 PBGA PR25D transistor on 4409 307-45 4946 ah lm 458 ic PDF

    transistor pt36c

    Abstract: datasheet transistor pt36C PT35c transistor pt36c microprocessor block diagram of plc pt35c transistor pt42c PT42C transistor BC 157 PLC Communication cables pin diagram
    Text: Data Sheet November, 2003 ORCA Series 4 FPGAs Introduction • Traditional I/O selections: — LVTTL 3.3V and LVCMOS (2.5 V and 1.8 V) I/Os. — Per pin-selectable I/O clamping diodes provide 3.3 V PCI compliance. — Individually programmable drive capability:


    Original     		sink/12 transistor pt36c datasheet transistor pt36C PT35c transistor pt36c microprocessor block diagram of plc pt35c transistor pt42c PT42C transistor BC 157 PLC Communication cables pin diagram PDF

    Untitled

    Abstract: No abstract text available
    Text: LatticeSC/M Family Data Sheet DS1004 Version 02.1, June 2008 LatticeSC/M Family Data Sheet Introduction January 2008 Data Sheet DS1004 Features • High Performance FPGA Fabric • 15K to 115K four input Look-up Tables LUT4s • 139 to 942 I/Os • 700MHz global clock; 1GHz edge clocks


    Original     		DS1004 DS1004 700MHz 600Mbps 125Gbps) 105mW PDF

    AD30102

    Abstract: E3P15
    Text: ORCA ORT42G5 and ORT82G5 06 to 3.7 Gbits/s XAUI and FC FPSCs March 2004 Data Sheet Introduction Lattice Semiconductor has developed a family of next generation FPSCs intended for high-speed serial backplane data transmission. Built on the Series 4 reconfigurable embedded System-on-a-Chip SoC architecture, the


    Original     		ORT42G5 ORT82G5 ORT82G5 ORT42G5-2BM484I ORT42G5-1BM484I ORT82G5-2BM680I ORT82G5-1BM680I AD30102 E3P15 PDF

    Untitled

    Abstract: No abstract text available
    Text: LatticeSC Family Data Sheet DS1004 Version 01.4b, February 2007 LatticeSC Family Data Sheet Introduction November 2006 Preliminary Data Sheet DS1004 Features • High Performance FPGA Fabric • 15K to 115K four input Look-up Tables LUT4s • 132 to 942 I/Os


    Original     		DS1004 DS1004 700MHz 600Mbps 125Gbps) 105mW SC115 PDF

    ORCA ORT42G5

    Abstract: No abstract text available
    Text: ORCA ORT42G5 and ORT82G5 3.7 Gbits/s XAUI and 4.25 Gbits/s FC FPSCs November 2003 Data Sheet Introduction Lattice Semiconductor has developed a family of next generation FPSCs intended for high-speed serial backplane data transmission. Built on the Series 4 reconfigurable embedded System-on-a-Chip SoC architecture, the


    Original     		ORT42G5 ORT82G5 ORT82G5 ORT42G5-2BM484ES ORT42G5-1BM484ES ORT82G5-2BM680I ORT82G5-1BM680I ORCA ORT42G5 PDF

    Untitled

    Abstract: No abstract text available
    Text: LatticeSC/M Family Data Sheet DS1004 Version 01.6, August 2007 LatticeSC/M Family Data Sheet Introduction March 2007 Preliminary Data Sheet DS1004 Features • High Performance FPGA Fabric • 15K to 115K four input Look-up Tables LUT4s • 132 to 942 I/Os


    Original     		DS1004 DS1004 700MHz 600Mbps 125Gbps) 105mW PDF

    AL437

    Abstract: L97c L235C L103T L41C L140C L94C l165c L239C L43C
    Text: ORCA ORSPI4 Dual SPI4 Interface and High-Speed SERDES FPSC November 2003 Preliminary Data Sheet Lattice Semiconductor has developed a next-generation FPSC targeted at high-speed data transmission. Built on the Series 4 reconfigurable embedded System-on-a-Chip SoC architecture, the ORSPI4 FPSC contains two


    Original     		8b/10b OIF-SPI4-02 ORSPI4-1FE1036IES ORSPI4-F1156IES ORSPI4-2FE1036CES ORSPI4-1FE1036CES ORSPI4-2F1156CES ORSPI4-1F1156CES AL437 L97c L235C L103T L41C L140C L94C l165c L239C L43C PDF

    L67c

    Abstract: L41C l44c L71C l75c transistor l57c IC L44C DATASHEET l31c L47c l51c
    Text: ORCA ORT42G5 and ORT82G5 06 to 3.7 Gbits/s XAUI and FC FPSCs February 2004 Data Sheet Introduction Lattice Semiconductor has developed a family of next generation FPSCs intended for high-speed serial backplane data transmission. Built on the Series 4 reconfigurable embedded System-on-a-Chip SoC architecture, the


    Original     		ORT42G5 ORT82G5 ORT82G5 ORT42G5-2BM484ES ORT42G5-1BM484ES ORT82G5-2BM680I ORT82G5-1BM680I ORT42G5 L67c L41C l44c L71C l75c transistor l57c IC L44C DATASHEET l31c L47c l51c PDF

    l37c 8 pin

    Abstract: L41C G40TL l34c L43C L74c L18T l14c L25C ENCODER l31c
    Text: ORCA ORT42G5 and ORT82G5 0.6 to 3.7 Gbps XAUI and FC FPSCs July 2008 Data Sheet DS1027 Introduction Lattice Semiconductor has developed a family of next generation FPSCs intended for high-speed serial backplane data transmission. Built on the Series 4 reconfigurable embedded System-on-a-Chip SoC architecture, the


    Original     		ORT42G5 ORT82G5 DS1027 ORT82G5 1-800-LATTICE BM680 9A-08. l37c 8 pin L41C G40TL l34c L43C L74c L18T l14c L25C ENCODER l31c PDF

    TL 2272 DECODER

    Abstract: 10G BERT TL 2262 L36CA 30132 verilog code 16 bit LFSR in PRBS 10gbps serdes 30014 ap13.6 diode 680-pin
    Text: Data Sheet April, 2002 ORCA ORT82G5 1.0—1.25/2.0—2.5/3.125—3.5 Gbits/s 8b/10b SERDES Backplane Interface FPSC Introduction Lattice has developed a next generation FPSC intended for high-speed serial backplane data transmission. Built on the Series 4 reconfigurable embedded system-on-chips SoC architecture, the


    Original     		ORT82G5 8b/10b ORT82G5 ORT82G53BM680-DB ORT82G52BM680-DB ORT82G51BM680-DB DS01-294NCIP DS01-218NCIP) TL 2272 DECODER 10G BERT TL 2262 L36CA 30132 verilog code 16 bit LFSR in PRBS 10gbps serdes 30014 ap13.6 diode 680-pin PDF

    L130C

    Abstract: L74c l31c l97c l65c A311TC l146c l48c L202C L235C
    Text: ORCA ORSPI4 Dual SPI4 Interface and High-Speed SERDES FPSC May 2009 Data Sheet Lattice Semiconductor has developed a next-generation FPSC targeted at high-speed data transmission. Built on the Series 4 reconfigurable embedded System-on-a-Chip SoC architecture, the ORSPI4 FPSC contains two


    Original     		8b/10b OIF-SPI4-02 1156-fpBGA 1036-ball 6A-07 1036fpSBGA 1036-ftSBGA) 06x-09 1036-pin 1036-pin L130C L74c l31c l97c l65c A311TC l146c l48c L202C L235C PDF

    transistor pt36c

    Abstract: pt36c PT35c transistor INTEL Core i5 760 PB7D pt35c k72 w5 OR3L165B8BM680-DB PB27A AL962
    Text: Data Addendum March 2002 ORCA OR3LxxxB Series Field-Programmable Gate Arrays Introduction • ■ Features ■ ■ ■ ■ ■ ■ ■ ■ High-performance, cost-effective, 0.25 µm 5-level metal technology. 2.5 V internal supply voltage and 3.3 V I/O supply


    Original     		16-bit OR3L165B7BC432I-DB OR3L165B7BM680I-DB OR3L225B7BC432I-DB1 OR3L225B7BM680I-DB1 DA99-011FPGA DA99-008FPGA DS99-087FPGA) transistor pt36c pt36c PT35c transistor INTEL Core i5 760 PB7D pt35c k72 w5 OR3L165B8BM680-DB PB27A AL962 PDF

    2-bit comparator

    Abstract: LFSC3GA15E-5F900I PR77A PR55D pr94a diode transistor pt36c pt36C PB110C pb127d PB138
    Text: LatticeSC/M Family Data Sheet DS1004 Version 01.8, November 2007 LatticeSC/M Family Data Sheet Introduction March 2007 Preliminary Data Sheet DS1004 Features • High Performance FPGA Fabric • 15K to 115K four input Look-up Tables LUT4s • 132 to 942 I/Os


    Original     		DS1004 DS1004 700MHz 600Mbps 125Gbps) 105mW 2-bit comparator LFSC3GA15E-5F900I PR77A PR55D pr94a diode transistor pt36c pt36C PB110C pb127d PB138 PDF

    Untitled

    Abstract: No abstract text available
    Text: LatticeSC Family Data Sheet DS1004 Version 01.5, March 2007 LatticeSC Family Data Sheet Introduction March 2007 Preliminary Data Sheet DS1004 Features • High Performance FPGA Fabric • 15K to 115K four input Look-up Tables LUT4s • 132 to 942 I/Os • 700MHz global clock; 1GHz edge clocks


    Original     		DS1004 DS1004 700MHz 600Mbps 125Gbps) 105mW LFSC25 FF1020 LFSC80 PDF

    2N3906 A30

    Abstract: relay5v ak25p 24c166 debounce IC M33 fuse B27 fuse n20 fuse PT25D C42 GORE
    Text: ORSO/ORT82G5 1 Rev. 1/7/03 Lattice Semiconductor Corp. JP4 Schematic page 3 A 7-pin serial connector used for configuration. Serial Connector Pin 1 Pin 2 Pin 3 Pin 4 Pin 5 Pin 6 Pin 7 GND NC PROGRMN DONE D0 CCLK VDD JP6 Schematic page 3 JP6 is an 8-pin JTAG connector. It is physically similar to JP4; an arrow indicates pin 1.


    Original     		ORSO/ORT82G5 22ufd 10ufd AMS1505 2N3906 A30 relay5v ak25p 24c166 debounce IC M33 fuse B27 fuse n20 fuse PT25D C42 GORE PDF

    Untitled

    Abstract: No abstract text available
    Text:  MachXO2 Breakout Board Evaluation Kit User’s Guide January 2014 Revision: EB68_02.2  MachXO2 Breakout Board Evaluation Kit User’s Guide Introduction Thank you for choosing the Lattice Semiconductor MachXO2 Breakout Board Evaluation Kit! This user’s guide describes how to start using the MachXO2 Breakout Board, an easy-to-use platform for evaluating and designing with the MachXO2 ultra-low density FPGA. Along with the board and accessories, this kit


    Original     		MachXO2-7000HE MachXO2-12R16, RC0603JR-070RL CRCW06031R00JNEAHP RC0603FR-07100RL RC0402FR-071KL FT2232HL 93LC56C-I/SN LCMXO2-7000HE-4TG144C PDF

    PL23B

    Abstract: CORE F5A pt35c 104 00 54407 1 PR25D
    Text: ORCA OR3LxxxB Series Device Datasheet June 2010 All Devices Discontinued! Product Change Notifications PCNs have been issued to discontinue all devices in this data sheet. The original datasheet pages have not been modified and do not reflect those changes.


    Original     		OR3L165B8PS208-DB OR3L165B7PS208-DB OR3L165B7PS208I-DB OR3L165B8PS240-DB OR3L165B7PS240-DB OR3L165B7PS240I-DB OR3L165B8BA352-DB OR3L165B7BA352-DB OR3L165B7BA352I-DB OR3L165B8BC432-DB PL23B CORE F5A pt35c 104 00 54407 1 PR25D PDF

    PB68C

    Abstract: LFSCM3GA40EP1
    Text: LatticeSC Family Data Sheet DS1004 Version 01.4a, January 2007 LatticeSC Family Data Sheet Introduction November 2006 Preliminary Data Sheet DS1004 Features • High Performance FPGA Fabric • 15K to 115K four input Look-up Tables LUT4s • 132 to 942 I/Os


    Original     		DS1004 DS1004 700MHz 600Mbps 125Gbps) 105mW LVPECL33 SC115 PB68C LFSCM3GA40EP1 PDF

    484-pin BGA

    Abstract: JC-115
    Text: ORCA ORT42G5 and ORT82G5 0.6 to 3.7 Gbits/s XAUI and FC FPSCs March 2003 Data Sheet Introduction Lattice Semiconductor has developed a family of next generation FPSCs intended for high-speed serial backplane data transmission. Built on the Series 4 reconfigurable embedded System-on-a-Chip SoC architecture, the


    Original     		ORT42G5 ORT82G5 ORT82G5 ORT42G5-2BM484I ORT42G5-1BM484I ORT82G5-2BM680I ORT82G5-1BM680I 484-pin BGA JC-115 PDF

    L43T

    Abstract: No abstract text available
    Text: ORCA ORT42G5 and ORT82G5 06 to 3.7 Gbits/s XAUI and FC FPSCs November 2007 Data Sheet DS1027 Introduction Lattice Semiconductor has developed a family of next generation FPSCs intended for high-speed serial backplane data transmission. Built on the Series 4 reconfigurable embedded System-on-a-Chip SoC architecture, the


    Original     		ORT42G5 ORT82G5 DS1027 ORT82G5 ORT42G5-2BMN484I ORT42G5-1BMN484I ORT82G5-2FN680I L43T PDF