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    Text: AVG Semiconductors_ DDiT 112 Technical Data Dual JK Negative Edge-Triggered Flip-Flops DV74LS112A PV74ALS112A N Suffix Plastic DIP AVG-003 Case This device contains two individual J, K, clock, and asynchronous set and clear inputs to each flip-flop. When the clock pulse goes


    OCR Scan     		DV74LS112A PV74ALS112A AVG-003 1-800-AVG-SEMI DV74LS112A, DV74ALS112A LS112A PDF