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Intel Corporation EPCQ16ASI8N IC CONFIG DEVICE 16MBIT 8SOIC
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DigiKey	EPCQ16ASI8N	Tube	27,273		1	1 $12.45 10 $12.45 100 $12.45 1000 $12.45 10000 $12.45	Buy Now
TME	EPCQ16ASI8N		1		1	1 $17.6 10 $17.2 100 $12.7 1000 $12.7 10000 $12.7	Buy Now
Ameya Holding Limited	EPCQ16ASI8N		93			1 - 10 - 100 - 1000 - 10000 -	Get Quote
Chip-Germany GmbH	EPCQ16ASI8N		4			1 - 10 - 100 - 1000 - 10000 -	Get Quote
Win Source Electronics	EPCQ16ASI8N		6,000			1 - 10 $11.4286 100 $9.2857 1000 $9.2857 10000 $9.2857	Buy Now
BYTe Semiconductor BY25Q16AWTIG(T) IC FLASH 16MBIT SPI/QUAD 8SOP
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DigiKey	BY25Q16AWTIG(T)	Tube	9,990		1	1 $0.63 10 $0.389 100 $0.2517 1000 $0.1754 10000 $0.1437	Buy Now
BYTe Semiconductor BY25Q16AWSIG(T) IC FLASH 16MBIT SPI/QUAD 8SOP
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DigiKey	BY25Q16AWSIG(T)	Tube	9,498		1	1 $0.86 10 $0.535 100 $0.86 1000 $0.26374 10000 $0.20055	Buy Now
BYTe Semiconductor BY25Q16AWTIG(R) 16 MBIT, WIDE VCC (1.7V TO 3.6V)
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DigiKey	BY25Q16AWTIG(R)	Digi-Reel	3,702		1	1 $0.26 10 $0.254 100 $0.2083 1000 $0.19715 10000 $0.19715	Buy Now
	BY25Q16AWTIG(R)	Cut Tape	3,702		1	1 $0.26 10 $0.254 100 $0.2083 1000 $0.19715 10000 $0.19715	Buy Now
E-T-A 3130-F110-P7T1-W01Q-16A CIR BRKR THRM 16A 250VAC 50VDC
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DigiKey	3130-F110-P7T1-W01Q-16A	Bulk	18		1	1 $28.95 10 $28.95 100 $16.9166 1000 $13.975 10000 $13.975	Buy Now
Mouser Electronics	3130-F110-P7T1-W01Q-16A		11			1 $27.75 10 $22.15 100 $16.91 1000 $13.97 10000 $13.97	Buy Now
Master Electronics	3130-F110-P7T1-W01Q-16A		25			1 $27.84 10 $24.85 100 $15.32 1000 $14.07 10000 $14.07	Buy Now
Sager	3130-F110-P7T1-W01Q-16A				10	1 - 10 $32.3 100 $22.05 1000 $15.49 10000 $15.49	Buy Now

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Q16A Datasheets Context Search

Catalog Datasheet	MFG & Type	Document Tags	PDF
MC14517 Abstract: 14517B Q32B Q32A Text: MC14517B Dual 64-Bit Static Shift Register The MC14517B dual 64−bit static shift register consists of two identical, independent, 64−bit registers. Each register has separate clock and write enable inputs, as well as outputs at bits 16, 32, 48, and 64. Data	Original	MC14517B 64-Bit 16-bit, 32-bit, 48-bit MC14517B/D MC14517 14517B Q32B Q32A	PDF
jfet j102 Abstract: SLUA372 tda 0470 bq78PL118EVM SLUA524 SLUU481 smd zener diode code z4 USB-TO-GPIO cell balance board users guide Advanced Gas Gauge Host Firmware Guide Text: User's Guide SLUU474 – January 2011 bq78PL116EVM Evaluation Module The bq78PL116EVM Evaluation Module can assist users in evaluating the bq78PL116 PowerLAN Master Gateway Controller. Included in this document are discussions of the board and its operation, the	Original	SLUU474 bq78PL116EVM bq78PL116 jfet j102 SLUA372 tda 0470 bq78PL118EVM SLUA524 SLUU481 smd zener diode code z4 USB-TO-GPIO cell balance board users guide Advanced Gas Gauge Host Firmware Guide	PDF
SFH-1212A Abstract: SFH-1212 diode c72 SFH 30A smd schottky diode s4 SOD-123 pwm e-bike laptop LCD SCHEMATIC Text: bq78PL116 SLUSAB8B – OCTOBER 2010 – REVISED FEBRUARY 2011 www.ti.com PowerLAN Master Gateway Battery Management Controller With PowerPump™ Cell Balancing Technology Check for Samples: bq78PL116 FEATURES 1 • 23 • • • • • • • • •	Original	bq78PL116 16-Series-Cell bq76PL102 SFH-1212A SFH-1212 diode c72 SFH 30A smd schottky diode s4 SOD-123 pwm e-bike laptop LCD SCHEMATIC	PDF
DDR2-667 Abstract: SSTUA32864 SSTUA32866 SSTUA32S865 TFBGA160 Text: SSTUA32S865 1.8 V 28-bit 1 : 2 registered buffer with parity for DDR2-667 RDIMM applications Rev. 02 — 16 March 2007 Product data sheet 1. General description The SSTUA32S865 is a 1.8 V 28-bit 1 : 2 register specifically designed for use on two rank by four 2R x 4 and similar high-density Double Data Rate 2 (DDR2) memory	Original	SSTUA32S865 28-bit DDR2-667 SSTUA32S865 14-bit DDR2-667 SSTUA32864 SSTUA32866 TFBGA160	PDF
SSTUA32864 Abstract: SSTUA32866 Text: SSTUG32868 1.8 V 28-bit 1 : 2 configurable registered buffer with parity for DDR2-1G RDIMM applications Rev. 01 — 23 April 2007 Product data sheet 1. General description The SSTUG32868 is a 1.8 V 28-bit 1 : 2 register specifically designed for use on two rank	Original	SSTUG32868 28-bit SSTUG32868 14-bit SSTUA32864 SSTUA32866	PDF
DDR2-800 Abstract: SSTUA32864 SSTUA32866 E6G3 Text: SSTUM32868 1.8 V 28-bit 1 : 2 configurable registered buffer with parity for DDR2-800 RDIMM applications Rev. 02 — 2 March 2007 Product data sheet 1. General description The SSTUM32868 is a 1.8 V 28-bit 1 : 2 register specifically designed for use on two rank	Original	SSTUM32868 28-bit DDR2-800 SSTUM32868 14-bit SSTUA32864 SSTUA32866 E6G3	PDF
Untitled Abstract: No abstract text available Text: 74SSTUB32868A www.ti.com SCAS846B – JULY 2007 – REVISED NOVEMBER 2007 28-BIT TO 56-BIT REGISTERED BUFFER WITH ADDRESS-PARITY TEST FEATURES 1 • Member of the Texas Instruments Widebus+ Family • Pinout Optimizes DDR2 DIMM PCB Layout • 1-to-2 Outputs Support Stacked DDR2 DIMMs	Original	74SSTUB32868A SCAS846B 28-BIT 56-BIT	PDF
Untitled Abstract: No abstract text available Text: 74SSTUB32868 www.ti.com . SCAS835C – JUNE 2007 – REVISED MARCH 2009 28-BIT TO 56-BIT REGISTERED BUFFER WITH ADDRESS-PARITY TEST	Original	74SSTUB32868 SCAS835C 28-BIT 56-BIT	PDF
J2 Q24A B Abstract: ICS98ULPA877A ICSSSTUAF32868A IDTCSPUA877A Q17A-Q20A Text: DATASHEET 28-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 Description ICSSSTUAF32868A QERR pin active low . The convention is even parity, i.e., valid parity is defined as an even number of ones across the DIMM-independent data inputs combined with the parity	Original	28-BIT ICSSSTUAF32868A before284 199707558G J2 Q24A B ICS98ULPA877A ICSSSTUAF32868A IDTCSPUA877A Q17A-Q20A	PDF
HD74SSTV32852 Abstract: HD74SSTV32852LBEL Q13A Text: To all our customers Regarding the change of names mentioned in the document, such as Hitachi Electric and Hitachi XX, to Renesas Technology Corp. The semiconductor operations of Mitsubishi Electric and Hitachi were transferred to Renesas Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog	Original	D-85622 D-85619 HD74SSTV32852 HD74SSTV32852LBEL Q13A	PDF
7103 Abstract: ICS98ULPA877A IDT74SSTUBH32865A IDTCSPUA877A Q19A Text: DATASHEET IDT74SSTUBH32865A 28-BIT 1:2 REGISTERED BUFFER FOR DDR2 Description The IDT74SSTUBH32865A includes a parity checking function. The IDT74SSTUBH32865A accepts a parity bit from the memory controller at its input pin PARIN, compares it with the data received on the D-inputs and	Original	IDT74SSTUBH32865A 28-BIT IDT74SSTUBH32865A CLK284 199707558G 7103 ICS98ULPA877A IDTCSPUA877A Q19A	PDF
SN74SSTV32852-EP Abstract: No abstract text available Text: SN74SSTV32852-EP 24-BIT TO 48-BIT REGISTERED BUFFER WITH SSTL_2 INPUTS AND OUTPUTS w w w .t i.c om SCES700 – OCTOBER 2007 FEATURES 1 • Controlled Baseline – One Assembly/Test Site, One Fabrication Site • Extended Temperature Performance of –40°C	Original	SN74SSTV32852-EP 24-BIT 48-BIT SCES700 SN74SSTV32852-EP	PDF
ICS98ULPA877A Abstract: IDT74SSTUBF32868A IDTCSPUA877A Q22B Text: DATASHEET 28-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 Description occurred on the open-drain QERR pin active low . The convention is even parity, i.e., valid parity is defined as an even number of ones across the DIMM-independent data inputs combined with the parity input bit. To calculate parity,	Original	28-BIT cyc284 199707558G ICS98ULPA877A IDT74SSTUBF32868A IDTCSPUA877A Q22B	PDF
Q32B Abstract: 14517B 14517B/BEAJC Text: MC14517B Dual 64−Bit Static Shift Register The MC14517B dual 64−bit static shift register consists of two identical, independent, 64−bit registers. Each register has separate clock and write enable inputs, as well as outputs at bits 16, 32, 48, and 64. Data	Original	MC14517B 64-Bit 16-bit, 32-bit, 48-bit 16-BIT 17-BIT Q32B 14517B 14517B/BEAJC	PDF

74SSTUB32865 Abstract: 74SSTUB32865ZJBR Q19A Text: 74SSTUB32865 www.ti.com SLAS537 – NOVEMBER 2007 28-BIT TO 56-BIT REGISTERED BUFFER WITH ADDRESS-PARITY TEST FEATURES 1 • Member of the Texas Instruments Widebus+ Family • Pinout Optimizes DDR2 RDIMM PCB Layout • 1-to-2 Outputs Supports Stacked DDR2	Original	74SSTUB32865 SLAS537 28-BIT 56-BIT 74SSTUB32865 74SSTUB32865ZJBR Q19A	PDF
14517B Abstract: MC14517B MC14517BCP MC14517BDW MC14517BDWR2 Text: MC14517B Dual 64-Bit Static Shift Register The MC14517B dual 64–bit static shift register consists of two identical, independent, 64–bit registers. Each register has separate clock and write enable inputs, as well as outputs at bits 16, 32, 48, and 64. Data	Original	MC14517B 64-Bit MC14517B r14525 MC14517B/D 14517B MC14517BCP MC14517BDW MC14517BDWR2	PDF
SLG8SP553V Abstract: KB926 LA4101P SP8K10 LM 4863 D FBMA-L11-201209-221LMA30T 4101p ich9 JMB385 compal notebook schematics Text: A B C D E 1 1 Compal confidential 2 2 Schematics Document Mobile Penryn uFCPGA with Intel Cantiga_GM+ICH9-M core logic 3 3 2008-01-01 4 4 Compal Secret Data Security Classification 2007/08/28 Issued Date 2006/03/10 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL	Original	4101P SLG8SP553V KB926 LA4101P SP8K10 LM 4863 D FBMA-L11-201209-221LMA30T 4101p ich9 JMB385 compal notebook schematics	PDF
74SSTUB32868A Abstract: 74SSTUB32868AZRHR Q13A D1-D28 Text: 74SSTUB32868A www.ti.com. SCAS846C – JULY 2007 – REVISED MARCH 2009 28-BIT TO 56-BIT REGISTERED BUFFER WITH ADDRESS-PARITY TEST	Original	74SSTUB32868A SCAS846C 28-BIT 56-BIT 74SSTUB32868A 74SSTUB32868AZRHR Q13A D1-D28	PDF
SFH-1212 Abstract: smd schottky diode s4 SOD-123 pwm e-bike P13S Text: bq78PL116 www.ti.com SLUSAB8A – OCTOBER 2010 – REVISED OCTOBER 2010 PowerLAN Master Gateway Battery Management Controller With PowerPump™ Cell Balancing Technology Check for Samples: bq78PL116 FEATURES 1 • 23 • • • • • • • • •	Original	bq78PL116 16-Series-Cell bq76PL102 SFH-1212 smd schottky diode s4 SOD-123 pwm e-bike P13S	PDF
Untitled Abstract: No abstract text available Text: 74SSTUB32868A www.ti.com. SCAS846C – JULY 2007 – REVISED MARCH 2009 28-BIT TO 56-BIT REGISTERED BUFFER WITH ADDRESS-PARITY TEST	Original	74SSTUB32868A SCAS846C 28-BIT 56-BIT	PDF
Untitled Abstract: No abstract text available Text: ICSSSTV32852 Integrated Circuit Systems, Inc. Preliminary Product Preview DDR 24-Bit to 48-Bit Registered Buffer Recommended Application: • DDR Memory Modules • Provides complete DDR DIMM logic solution with ICS93V857 or ICS95V857 • SSTL_2 compatible data registersProduct	Original	ICSSSTV32852 24-Bit 48-Bit ICS93V857 ICS95V857 114-Pin -310mV 0513C--06/07/02 ICSSSTV32852y	PDF
Untitled Abstract: No abstract text available Text: SSTUB32868 1.8 V 28-bit 1 : 2 configurable registered buffer with parity for DDR2-800 RDIMM applications Rev. 04 — 22 April 2010 Product data sheet 1. General description The SSTUB32868 is a 1.8 V 28-bit 1 : 2 register specifically designed for use on two rank	Original	SSTUB32868 28-bit DDR2-800 SSTUB32868 14-bit	PDF
Untitled Abstract: No abstract text available Text: SSTUM32865 1.8 V 28-bit 1 : 2 registered buffer with parity for DDR2-800 RDIMM applications Rev. 01 — 19 September 2007 Product data sheet 1. General description The SSTUM32865 is a 1.8 V 28-bit 1 : 2 register specifically designed for use on two rank by four 2R x 4 and similar high-density Double Data Rate 2 (DDR2) memory modules. It	Original	SSTUM32865 28-bit DDR2-800 SSTUM32865 14-bit	PDF
Untitled Abstract: No abstract text available Text: C O S/M O S INTEGRATED CIRCUIT , hcc/ hcf «17B DUAL 64-STAGE STATIC SH IFT REGISTER • • • • • • • • • CLO C K FR EQ UENC Y 12 MHz TYP. A T V DD= 10V S C H M IT T T R IG G E R CLOCK INPUTS A L L O W O PE R ATIO N W ITH V E R Y SLOW CLO CK RISE	OCR Scan	64-STAGE	PDF

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Q16A Price and Stock

Intel Corporation EPCQ16ASI8N

BYTe Semiconductor BY25Q16AWTIG(T)

BYTe Semiconductor BY25Q16AWSIG(T)

BYTe Semiconductor BY25Q16AWTIG(R)

E-T-A 3130-F110-P7T1-W01Q-16A

Q16A Datasheets Context Search

MC14517

jfet j102

SFH-1212A

DDR2-667

SSTUA32864

DDR2-800

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J2 Q24A B

HD74SSTV32852

7103

SN74SSTV32852-EP

ICS98ULPA877A

Q32B

74SSTUB32865

14517B

SLG8SP553V

74SSTUB32868A

SFH-1212

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