QUICKLOGIC 2001 Search Results

QUICKLOGIC 2001 Result Highlights (5)

Part	Manufacturer	Description	Download
CO-142BNCX200-100	Amphenol Cables on Demand	Amphenol CO-142BNCX200-100 BNC Male to BNC Male (RG142) 50 Ohm Coaxial Cable Assembly (High-Temp Teflon RG142B/U) 100ft	Datasheet
FO-10GGBLCX20-010	Amphenol Cables on Demand	Amphenol FO-10GGBLCX20-010 LC-LC Duplex 10Gb Multimode 50/125 OM3 Fiber Optic Patch Cable - 2 x LC Male to 2 x LC Male 10m	Datasheet
CO-174RASMAX2-001	Amphenol Cables on Demand	Amphenol CO-174RASMAX2-001 SMA Right Angle Male to SMA Right Angle Male (RG174) 50 Ohm Coaxial Cable Assembly 1ft	Datasheet
CS-SATDRIVEX2-001	Amphenol Cables on Demand	Amphenol CS-SATDRIVEX2-001 Serial ATA Extension Cable - SATA II Drive Extension Cable with Power (6.0 Gbps) 1m	Datasheet
CO-058BNCX200-100	Amphenol Cables on Demand	Amphenol CO-058BNCX200-100 BNC Male to BNC Male (RG58) 50 Ohm Coaxial Cable Assembly 100ft	Datasheet

QUICKLOGIC 2001 Datasheets Context Search

Catalog Datasheet	MFG & Type	Document Tags	PDF
V321USC Abstract: MIPS bus architecture mips embedded processor quicklogic 2001 Text: Hardware Support Components QuickLogic Corporation V321USC PCI System Controller QuickLogic Corporation CPUs Supported R5xxx Product Description The V321USC Universal System Controller is a thirdgeneration PCI product that integrates many functions needed in typical embedded systems. The USC reduces	Original	V321USC 64-bit 32-bit MIPS bus architecture mips embedded processor quicklogic 2001	PDF
VR5500 Abstract: MIPS 32-bit bus architecture MIPS data bus V340HPC RM7000 VR5000 pci 32 bit 5v nec vr5500 pci non-transparent bridge Text: Hardware Support Components QuickLogic Corporation V340HPC PCI System Controller QuickLogic Corporation Features • Fully compliant with PCI Local Bus Specification, Revision 2.2 • Configurable for a single 64-bit PCI bus or dual 32-bit PCI buses • Up to 100 MHz local bus supports an external cache	Original	V340HPC 64-bit 32-bit 32-bit VR5500 MIPS 32-bit bus architecture MIPS data bus RM7000 VR5000 pci 32 bit 5v nec vr5500 pci non-transparent bridge	PDF
MorethanIP Abstract: QL82SD vhdl code for phy interface Text: Utopia Level 2 Slave Interface Macrocell For Quicklogic Eclipse and QuickSD ESP Product Brief Version 1.1 February 2001 Introduction The Utopia Universal Test & Operations PHY Interface for ATM interface is defined by the ATM Forum to provide a standard interface	Original	af-phy-0039 QL82SD MorethanIP vhdl code for phy interface	PDF
vhdl code for phy interface Abstract: OC48 QL82SD AF-PHY-0136 Text: Utopia Level 3 Slave Interface Macrocell For Quicklogic Eclipse and QuickSD ESP Product Brief Version 1.0 February 2001 Exceeding OC48 requirements cell rate transfers Introduction The Utopia (Universal Test & Operations PHY Interface for ATM) interface is defined by the	Original	104MHz 32-Bit af-phy-0136 QL82SD vhdl code for phy interface OC48	PDF
UT4090 Abstract: QuickLogic Military FPGA Introduction Text: Standard Products UT4090 RadHard FPGA Advanced Data Sheet August 3, 2001, Rev D q Comprehensive design tools include high quality Verilog/ VHDL synthesis and simulation q QuickLogic existing IP such as microcontrollers, DRAM controllers, USART and PCI can be accessed	Original	UT4090 208-pin 16-bit QuickLogic Military FPGA Introduction	PDF
QL82SD Abstract: No abstract text available Text: Utopia Level 2 Master Interface Macrocell For Quicklogic Eclipse and QuickSD ESP Product Brief Version 1.1 February 2001 Introduction The Utopia Universal Test & Operations PHY Interface for ATM interface is defined by the ATM Forum to provide a standard interface	Original	af-phy-0039 QL82SD	PDF
QL82SD Abstract: vhdl code for 32bit data memory AF-PHY-0136 Text: Utopia Level 3 Master Interface Macrocell For Quicklogic Eclipse and QuickSD ESP Product Brief Version 1.1 February 2001 status indication and User programmable FIFO thresholds Introduction The Utopia Universal Test & Operations PHY Interface for ATM interface is defined by the	Original	af-phy-0136 QL82SD vhdl code for 32bit data memory	PDF
QL3012 Abstract: QL3025 QL3040 QL3060 QL4016 QL4090 footprint pqfp 208 QuickLogic Military FPGA Introduction Text: QuickLogic Military FPGA Introduction Military FPGA Combining High Performance and High Density Military FPGA Introduction DEVICE HIGHLIGHTS Device Highlights Military FPGA • Mil Std 883 and Mil Temp Ceramic ■ Mil Temp Plastic Guaranteed -55 to +125oC	Original	125oC 152-bit 16-bit -55oC, QL3012 QL3025 QL3040 QL3060 QL4016 QL4090 footprint pqfp 208 QuickLogic Military FPGA Introduction	PDF
asynchronous fifo vhdl Abstract: 8 BIT ALU design with verilog/vhdl code full subtractor using ic 74138 74139 for bcd to excess 3 code vhdl code for 8bit bcd to seven segment display 32 BIT ALU design with verilog/vhdl code 74594 16 BIT ALU design with verilog/vhdl code B1516 RAM1024 Text: QuickWorks User Manual with SpDE Reference Release 2009.2.1 Contact Information QuickLogic Corporation 1277 Orleans Drive Sunnyvale, CA 94089 Phone: (408) 990-4000 (US) (905) 940-4149 (Canada) +(44) 1932-57-9011 (Europe) +(852) 2567-5441 (Asia) E-mail: info@quicklogic.com	Original		PDF
BN27 Diode Abstract: BR28 BQ28 bn27 BM2-8 AR28 AQ27 bm28 BN28 BH27 Text: Application Note #59 •••••• Increasing Performance in QL82SD Channel Clock Mode Designs 1.0 Summary To operate the QL82SD QuickLogic SERDES device at higher speeds in the separate clock channel mode, a delay must be introduced in the transmit data and clock signals. This AppNote provides:	Original	QL82SD BN27 Diode BR28 BQ28 bn27 BM2-8 AR28 AQ27 bm28 BN28 BH27	PDF
AA10 Abstract: AA13 AA15 QL6250 QL6250-4PQ208C QL6250-4PS484C QL6250-4PT280C Text: QL6250 Eclipse Data Sheet • • • • • • Combining Performance, Density, and Embedded RAM Device Highlights Advanced Clock Network • Nine Global Clock Networks: Flexible Programmable Logic • 0.25 µm, Five layer metal CMOS Process • One Dedicated	Original	QL6250 304-bit AA10 AA13 AA15 QL6250-4PQ208C QL6250-4PS484C QL6250-4PT280C	PDF
Untitled Abstract: No abstract text available Text: QL5030 QuickPCI Data Sheet • • • • • • 33 MHz/32-bit PCI Target with Embedded Programmable Logic and Dual Port SRAM Device Highlights Programmable Logic • 24 K system gates/266 logic cells High Performance PCI Controller • 9,216 RAM bits and 71 I/O pins	Original	QL5030 Hz/32-bit 32-bit/33 95/98/2000/NT4 144-pin	PDF
eclipse Abstract: AA10 AA13 AA15 QL6325 QL6325-4PS484C QL6325-4PT280C Text: QL6325 Eclipse Data Sheet • • • • • • Combining Performance, Density, and Embedded RAM Device Highlights Advanced Clock Network • Nine Global Clock Networks: Flexible Programmable Logic • 0.25 µm, Five layer metal CMOS Process • One Dedicated	Original	QL6325 304-bit eclipse AA10 AA13 AA15 QL6325-4PS484C QL6325-4PT280C	PDF
Untitled Abstract: No abstract text available Text: QL3004 pASIC 3 FPGA Data Sheet •••••• 4,000 Usable PLD Gate pASIC 3 FPGA Combining High Performance and High Density Device Highlights High Performance & High Density • 4,000 Usable PLD Gates with 82 I/Os • 300 MHz 16-bit Counters, 400 MHz Datapaths	Original	QL3004 16-bit	PDF

QL3004 Abstract: QL3004-1PL68C PF100 PL84 PQ208 QL3012-1PF100C Text: QL3004 pASIC 3 FPGA Data Sheet •••••• 4,000 Usable PLD Gate pASIC 3 FPGA Combining High Performance and High Density Device Highlights High Performance & High Density • 4,000 Usable PLD Gates with 74 I/Os • 300 MHz 16-bit Counters, 400 MHz Datapaths	Original	QL3004 16-bit QL3004-1PL68C PF100 PL84 PQ208 QL3012-1PF100C	PDF
Untitled Abstract: No abstract text available Text: QL3025 pASIC 3 FPGA Data Sheet •••••• 25,000 Usable PLD Gate pASIC 3 FPGA Combining High Performance and High Density Device Highlights High Performance & High Density • 25,000 Usable PLD Gates with 204 I/Os • 300 MHz 16-bit Counters, 400 MHz Datapaths	Original	QL3025 16-bit	PDF
Untitled Abstract: No abstract text available Text: QL5332 QuickPCI Data Sheet • • • • • • 33 MHz/32-Bit PCI Master/Target with Embedded Programmable Logic and Dual Port SRAM Device Highlights High Performance PCI Controller QL5332 supports new enhanced features added to QL5032: • All PCI commands including configuration and	Original	QL5332 Hz/32-Bit QL5032: QL5032 32-bit/33	PDF
Untitled Abstract: No abstract text available Text: QL3040 pASIC 3 FPGA Data Sheet •••••• 40,000 Usable PLD Gate pASIC 3 FPGA Combining High Performance and High Density Device Highlights High Performance & High Density • 40,000 Usable PLD Gates with 252 I/Os • 300 MHz 16-bit Counters, 400 MHz Datapaths	Original	QL3040 16-bit	PDF
Untitled Abstract: No abstract text available Text: QL6250 Eclipse Data Sheet • • • • • • Combining Performance, Density, and Embedded RAM Device Highlights Advanced Clock Network • Nine Global Clock Networks: Flexible Programmable Logic • .25 µm, Five layer metal CMOS Process • One Dedicated	Original	QL6250 304-bit	PDF
QL3012 Abstract: No abstract text available Text: QL3012 pASIC 3 FPGA Data Sheet •••••• 12,000 Usable PLD Gate pASIC 3 FPGA Combining High Performance and High Density Device Highlights High Performance & High Density • 12,000 Usable PLD Gates with 118 I/Os • 300 MHz 16-bit Counters, 400 MHz Datapaths	Original	QL3012 16-bit	PDF
AA10 Abstract: AA13 AA15 QL6600 QL6600-4PS484C QL6600-4PT280C BC930 Text: QL6600 Eclipse Data Sheet • • • • • • Combining Performance, Density, and Embedded RAM Device Highlights Advanced Clock Network • Nine Global Clock Networks: Flexible Programmable Logic • 0.25 µm, Five layer metal CMOS Process • One Dedicated	Original	QL6600 304-bit AA10 AA13 AA15 QL6600-4PS484C QL6600-4PT280C BC930	PDF
QL3012-1PF144C Abstract: QL3012 PF100 PF144 PL84 PQ208 QL3012-1PF100C IO21 Text: QL3012 pASIC 3 FPGA Data Sheet •••••• 12,000 Usable PLD Gate pASIC 3 FPGA Combining High Performance and High Density Device Highlights High Performance & High Density • 12,000 Usable PLD Gates with 118 I/Os • 300 MHz 16-bit Counters, 400 MHz Datapaths	Original	QL3012 16-bit QL3012-1PF144C PF100 PF144 PL84 PQ208 QL3012-1PF100C IO21	PDF
Untitled Abstract: No abstract text available Text: QL3025 pASIC 3 FPGA Data Sheet •••••• 25,000 Usable PLD Gate pASIC 3 FPGA Combining High Performance and High Density Device Highlights High Performance & High Density • 25,000 Usable PLD Gates with 204 I/Os • 300 MHz 16-bit Counters, 400 MHz Datapaths	Original	QL3025 16-bit	PDF
QL5332-33APQ208C Abstract: PB256 PCI32 PQ208 QL5032 QL5332 82ad Text: QL5332 QuickPCI Data Sheet • • • • • • 33 MHz/32-Bit PCI Master/Target with Embedded Programmable Logic and Dual Port SRAM Device Highlights High Performance PCI Controller QL5332 supports new enhanced features added to QL5032: • All PCI commands including configuration and	Original	QL5332 Hz/32-Bit QL5032: QL5032 32-bit/33 QL5332-33APQ208C PB256 PCI32 PQ208 QL5032 82ad	PDF

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QUICKLOGIC 2001 Search Results

QUICKLOGIC 2001 Result Highlights (5)

QUICKLOGIC 2001 Datasheets Context Search

V321USC

VR5500

MorethanIP

vhdl code for phy interface

UT4090

QL82SD

QL82SD

QL3012

asynchronous fifo vhdl

BN27 Diode

AA10

Untitled

eclipse

Untitled

QL3004

Untitled

Untitled

Untitled

Untitled

QL3012

AA10

QL3012-1PF144C

Untitled

QL5332-33APQ208C