ring COUNTER
Abstract: AN-69 IDT72211 IDT72215 IDT72225
Text: Integrated Device Technology, Inc. DEPTH EXPANSION OF IDT'S SYNCHRONOUS FIFOs USING THE RING COUNTER APPROACH APPLICATION NOTE AN-69 By Bhanu V. R. Nanduri INTRODUCTION This application note describes a concise design approach to expand in depth IDT’s synchronous FIFOs. As an example
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AN-69
IDT72211
IDT72211
20R8s.
ring COUNTER
AN-69
IDT72215
IDT72225
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finder 15.21
Abstract: Z-636 sec 731 BEC10
Text: T1Mx28 Device DS1 Mapper 28-Channel TXC-04228 DATA SHEET SYSTEM SIDE Add Bus APPLICATIONS • SONET/SDH terminal or add/drop multiplexers supporting both asynchronous and byte-synchronous modes • Unidirectional or bidirectional ring applications • SONET remote digital terminal equipment
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T1Mx28
28-Channel
TXC-04228
VC-4/AU-3/TU-11)
5/TU-11
TXC-04228-MB
finder 15.21
Z-636
sec 731
BEC10
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ring synchronous COUNTER
Abstract: AN-728 C1995 DP83251 DP83261
Text: 1 0 INTRODUCTION The National DP83200 FDDI Chip Set includes special features that aid in the management of an FDDI station as well as the management of an FDDI ring An attempt is made here to guide you through some of the details of Station Management SMT using National’s DP83200 FDDI Chip
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DP83200
20-3A
ring synchronous COUNTER
AN-728
C1995
DP83251
DP83261
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MPEG 1 Audio Compression
Abstract: No abstract text available
Text: Advanced Micro Devices Multimedia Over FDDI Conference Paper Reprint 1992 IEEE, Reprinted with permission, from Proceedings of IEEE Local Computer Networks, Minneapolis, Sept. 13–15, 1992. 17386A Multimedia Over FDDI Amit Shah1 , Don Staddon2, Izhak Rubin3, Aleksandar Ratkovic4
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7386A
200km.
MPEG 1 Audio Compression
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7Pin din Connector
Abstract: 5300-26 kit nf 246
Text: Temposonics Magnetostrictive Linear-Position Sensors R-Series Model RP and RH Sensors Synchronous Serial Interface SSI Output 550989 D Product Specification • Rugged industrial sensor ■ Linear, absolute measurement ■ LEDs for sensor diagnostics ■ Non-contact sensing technology
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D-58513
7Pin din Connector
5300-26
kit nf 246
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four way traffic light controller vhdl coding
Abstract: DS638 traffic light controller vhdl coding XC3S1500-FG456 act30 application vhdl code for TRAFFIC LIGHT CONTROLLER SINGLE WAY act30 vhdl code for traffic light control microblaze locallink str 4512
Text: XPS MOST NIC v1.01a DS638 December 2, 2009 Product Specification Introduction LogiCORE IP Facts The LogiCORE Media Oriented Systems Transport (MOST ) Network Interface Controller (NIC) core is a controller designed to the MOST Specification revision
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DS638
four way traffic light controller vhdl coding
traffic light controller vhdl coding
XC3S1500-FG456
act30 application
vhdl code for TRAFFIC LIGHT CONTROLLER SINGLE WAY
act30
vhdl code for traffic light control
microblaze locallink
str 4512
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5p08
Abstract: M37542M4-XXXFP
Text: MITSUBISHI MICROCOMPUTERS RY A N IMI . ion. hange icat ecif ct to c p s al bje a fin are su not s is is ric limit h T met ice: Not e para Som PRE L 7542 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER DESCRIPTION APPLICATION The 7542 Group is the 8-bit microcomputer based on the 740 family core technology.
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16-bit
2002MITSUBISHI
5p08
M37542M4-XXXFP
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M37542M4V-XXXGP
Abstract: X1s Mitsubishi M37542M4-XXXFP
Text: To all our customers Regarding the change of names mentioned in the document, such as Mitsubishi Electric and Mitsubishi XX, to Renesas Technology Corp. The semiconductor operations of Hitachi and Mitsubishi Electric were transferred to Renesas Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog
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2002MITSUBISHI
M37542M4V-XXXGP
X1s Mitsubishi
M37542M4-XXXFP
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SUPERNET 2 Family
Abstract: AMD Supernet
Text: Advanced Micro Devices The Effect of Local Buffer Memory Size on FDDI Throughput by David Roberts Publication # 16294 Rev. Amendment A /0 Issue Date 1/92 1992 Advanced Micro Devices, Inc. The Effect of Local Buffer Memory Size on FDDI Throughput by David Roberts
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CY7C1367A
Abstract: GVT71512C18 4947a
Text: CY7C1366A/GVT71256C36 CY7C1367A/GVT71512C18 256K x 36/512K x 18 Synchronous Pipelined SRAM Features 18 SRAM cells with advanced synchronous peripheral circuitry and a 2-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a
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CY7C1366A/GVT71256C36
CY7C1367A/GVT71512C18
36/512K
100-Pin
1-85050-A
119-Lead
CY7C1367A
GVT71512C18
4947a
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CY7C1363A
Abstract: GVT71256B36 GVT71512B18 GVT71512B18TA-8
Text: 1CY7C1361A CY7C1361A/GVT71256B36 CY7C1363A/GVT71512B18 256K x 36/512K x 18 Synchronous Burst Flowthrough SRAM Features • • • • • • • • • • • • • • • • • • and a 2-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positiveedge-triggered Clock Input CLK . The synchronous inputs include all addresses, all data inputs, address-pipelining Chip
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1CY7C1361A
CY7C1361A/GVT71256B36
CY7C1363A/GVT71512B18
36/512K
CY7C1363A
GVT71256B36
GVT71512B18
GVT71512B18TA-8
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GVT71256B36T-7
Abstract: CY7C1363A GVT71256B36 GVT71512B18 926B1 a453t GVT71256B36TA
Text: 1CY7C1361A CY7C1361A/GVT71256B36 CY7C1363A/GVT71512B18 256K x 36/512K x 18 Synchronous Burst Flowthrough SRAM Features • • • • • • • • • • • • • • • • • • and a 2-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positiveedge-triggered Clock Input CLK . The synchronous inputs include all addresses, all data inputs, address-pipelining Chip
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1CY7C1361A
CY7C1361A/GVT71256B36
CY7C1363A/GVT71512B18
36/512K
clock2001.
GVT71256B36T-7
CY7C1363A
GVT71256B36
GVT71512B18
926B1
a453t
GVT71256B36TA
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CY7C1363A
Abstract: GVT71256B36 GVT71512B18
Text: CY7C1361A/GVT71256B36 CY7C1363A/GVT71512B18 256K x 36/512K x 18 Synchronous Burst Flowthrough SRAM Features • • • • • • • • • • • • • • • • • • and a 2-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positiveedge-triggered Clock Input CLK . The synchronous inputs include all addresses, all data inputs, address-pipelining Chip
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CY7C1361A/GVT71256B36
CY7C1363A/GVT71512B18
36/512K
CY7C1363A
GVT71256B36
GVT71512B18
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P5AC312-25
Abstract: D5AC312-25 D5AC312 N5AC324 p5ac312 N5AC312 P5AC312-30 D5AC32430 EP312DC-25 EP312PC-25
Text: April 1995, ver. 1 Features Data Sheet • ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ General Description Altera Corporation A-DS-312/324.01 EP312 & EP324 Classic EPLDs High-performance EPLDs with 12 macrocells EP312 or 24 macrocells (EP324)
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-DS-312/324
EP312
EP324
EP312)
EP324)
20-pin
P5AC312-25
D5AC312-25
D5AC312
N5AC324
p5ac312
N5AC312
P5AC312-30
D5AC32430
EP312DC-25
EP312PC-25
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LED04
Abstract: 450 khz ceramic filter Nippon capacitors
Text: PRELIMINARY Notice: This is not a final specification. Some parametric limits are subject to change. 7542 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER DESCRIPTION FEATURES • • • • • • • • • • Basic machine-language instructions . 71
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Untitled
Abstract: No abstract text available
Text: Preliminary GS88118/36T-11/11.5/100/80/66 100-Pin TQFP Commercial Temp Industrial Temp MHz 512K x 18, 256K x 36 ByteSafe 100 MHz–66 3.3 V VDD 8Mb Sync Burst SRAMs 3.3 V and 2.5 V I/O 1.11 9/2000Features counter may be configured to count in either linear or
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GS88118/36T-11/11
100-Pin
9/2000Features
3/2000N;
GS88118/36T1
3/2000O;
GS88118/36TRev1
9/1999I
NGS88118/36T1
2000O;
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pu 4119
Abstract: No abstract text available
Text: 191 54F/74F191 Connection Diagrams Up/Down Binary Counter W ith Preset and Ripple Clock Description The ’F191 is a reversible m odulo-16 binary c o u n te r fea tu ring synchronous co u n tin g and asynchronous presetting. The preset feature allow s the
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54F/74F191
odulo-16
54F/74F
pu 4119
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Untitled
Abstract: No abstract text available
Text: 190 54F/74F190 Connection Diagrams Up/Down Decade Counter With Preset and Ripple Clock Description The ’F190 is a reversible BCD 8421 decade co u n te r fea tu ring synchronous c o u n tin g and asynchronous presetting. The preset feature allow s the ’F190 to be used in program m able dividers. The C ount Enable
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54F/74F190
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D5AC32430
Abstract: D5AC312-30 D5AC312
Text: F e a tu re s G e Pie r a I . D e S C ri p t i o n Altera Corporation A-DS-312/324.01 High-performance EPLDs w ith 12 macrocells EP312 or 24 macrocells (EP324) - Combinatorial speeds as fast as 25 ns - Counter frequencies of up to 33.3 MHz - Pipelined data rates of up to 66 MHz
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EP312)
EP324)
20-pin
EP312
D5AC32430
D5AC312-30
D5AC312
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Cermetek ch1782
Abstract: RJ11C s22 varistor 1N914 2N2222 CH1782 CH1782SF TR302 modem v.22 wiring diagram for 5v solid state relay auto
Text: ŒRHETEK MICROELECTRONICS Cerm etek m leroslaecronles bflE D • 2GGSfl03 0DD1313 7TQ « C E R CH1782 — V.22 bis/2400 bps CH1782SF — With Send Fax Ultra Small Modem Module INTRODUCTION FEATURES The C H I 782 is the smallest full function 2400 bps modem
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2GGSfl03
0DD1313
CH1782
bis/2400
CH1782SF
indust964-0412
Cermetek ch1782
RJ11C
s22 varistor
1N914
2N2222
CH1782
CH1782SF
TR302
modem v.22
wiring diagram for 5v solid state relay auto
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DP83256
Abstract: DP83257 DP83261 DP83265 DP83266 AB8p DP83266 MACSI Device MAC layer sequence number
Text: NATL SEHICON]> LINEAR (□501124 QQÖ334S H2S bbE ]> PRELIMINARY DP83266 MACSI Device (FDDI Media Access Controller and System Interface) On-chip address bit swapping capability 32-bit wide Address/Data path with byte parity Programmable transfer burst sizes of 4 or 8
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DP83266
160-PIN
TL/F/11705-33
DP83256
DP83257
DP83261
DP83265
AB8p
DP83266 MACSI Device
MAC layer sequence number
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Untitled
Abstract: No abstract text available
Text: CERMETEK MICROELECTRONICS m lero« l«ecren les bflE D • 20GSfl03 Ü D D 1 3 1 3 7 tÌG « C E R CH1782 — V.22 bis/2400 bps CH1782SF — With Send Fax Ultra Small Modem Module INTRODUCTION FEATURES The CH1782 is the smallest full function 2400 bps modem
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20GSfl03
CH1782
bis/2400
CH1782SF
CH1782SF--
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ep512 dc
Abstract: No abstract text available
Text: ALTERA CORP EP512 S4E I> . • QST537S Ü001117 S I ' J. ■.* M 2 MACROCELL EPLD w w m m FEATURES GENERAL DESCRIPTION High Performance logic replacement for TTL and 74HC or 74HCT SSI and MSI logic. High Speed, tpd = 25ns, and 40MHz operating frequency. "Zero Power" 150 //A Standby Current .
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EP512
QST537S
74HCT
40MHz
0ST5372
QSTS37E
tAIL01
ep512 dc
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12M44
Abstract: No abstract text available
Text: dË MITSUBISHI -CDGTL LOGIC} TI ¿.i mi ISU131SHÍ 91D 12442 | b H M ^ ñ S ? _ {D G T L Q Ü 1E M 42 1 LOGIC MITSUBISHI ALSTTLs D M 74A LS190P SYNCHRONOUS PRESETTA BLE U P /D O W N DECADE COUNTER W IT H MODE CONTROL 7 ^ < /r T ? 3 -o < 3 DESCRIPTION
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ISU131SHÍ
LS190P
16P2P
16-PIN
150mil
T-90-20
20P2V
300mil
12M44
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