ROUT23 Search Results

DS90C124

Contextual Info: DS90C241 Serializer and DS90C124 Deserializer Evaluation Kit User’s Manual NSID: SERDES24-35USB Rev 1.5 National Semiconductor Corporation Date: 2/27/2008 Page 1 of 39 Table of Contents TABLE OF CONTENTS . 2

Contextual Info: D S 9 9 R 1 0 5 ,D S 9 9 R 1 0 6 DS99R105/DS99R106 3-40MHz DC-Balanced 24-Bit LVDS Serializer and Deserializer Texas INSTRUMENTS Literature Number: SNLS242C £/r Semiconductor D S 9 9 R 1 0 5 /D S 9 9 R 1 06 3 -4 0M H z D C -B alanced 2 4-B it LVD S S e ria lize r and

131-6 bj 025

Contextual Info: D S 9 9 R 1 0 3 ,D S 9 9 R 1 0 4 DS99R103/DS99R104 3-40MHz DC-Balanced 24-Bit LVDS Serializer and Deserializer Te x a s INSTRUMENTS Literature Number: SNLS241C a t i o n a l D S 9 9 R 1 0 3 /D S 9 9 R 1 04 3 -4 0M H z D C -B alanced 2 4-B it LVD S S e ria lize r and

Contextual Info: J t / i Texas " DS90UR907Q In s t r u m e n t s 5 - 6 5 MHz 24-bit Color FPD-Link to FPD-Link II Converter Features S 5 ± 65 MHz support 140 Mbps to 1.82 Gbps Serial Link Serial transmission is optimized by a user selectable de-emphasis and differential output level select features. EMI is

LVDS Cable STP

Contextual Info: DS99R103/DS99R104 3-40MHz DC-Balanced 24-Bit LVDS Serializer and Deserializer General Description • Internal DC Balancing encode/decode – Supports AC- The DS99R103/104 Chipset translates a 24-bit parallel bus into a fully transparent data/control LVDS serial stream with

digital video serializer

Abstract: Mini USB 5Pin mini USB B 5pin SERDES01-40USB 50-pin lcd connector pinout panel mount banana jack DIN11 DS99R101 VG-835 cable usb to idc 6 pin
Contextual Info: SERDES Evaluation Kit DS99R101/102 USB Version 0.1 Users Manual SERDES Demonstration Kit User Manual NSID: SERDES01-40USB DS99R101/102 Rev 0.1 National Semiconductor Corporation Date: 5/14/2008 Page 1 of 37 SERDES Evaluation Kit DS99R101/102 USB Version 0.1 Users Manual

DS90C124

Contextual Info: DS90C124, DS90C241 www.ti.com SNLS209K – NOVEMBER 2005 – REVISED SEPTEMBER 2011 DS90C241/DS90C124 5-35MHz DC-Balanced 24-Bit FPD-Link II Serializer and Deserializer Check for Samples: DS90C124, DS90C241 FEATURES 1 • 23 • • • • • 5 MHz–35 MHz clock embedded and DCBalancing 24:1 and 1:24 data transmissions

Contextual Info: DS99R103, DS99R104 www.ti.com SNLS241D – MARCH 2007 – REVISED APRIL 2013 DS99R103/DS99R104 3-40MHz DC-Balanced 24-Bit LVDS Serializer and Deserializer Check for Samples: DS99R103, DS99R104 FEATURES DESCRIPTION • The DS99R103/DS99R104 Chipset translates a 24bit parallel bus into a fully transparent data/control

DS90C124-Q1

Abstract: DS90C124
Contextual Info: DS90C124, DS90C241 www.ti.com SNLS209L – NOVEMBER 2005 – REVISED APRIL 2013 DS90C241 and DS90C124 5-MHz to 35-MHz DC-Balanced 24-Bit FPD-Link II Serializer and Deserializer Check for Samples: DS90C124, DS90C241 FEATURES DESCRIPTION • The DS90C241 and DS90C124 chipset translates a

"frame grabber"

Abstract: RHS36
Contextual Info: DS92LV0411, DS92LV0412 www.ti.com SNLS331B – MAY 2010 – REVISED APRIL 2013 DS92LV0411 / DS92LV0412 5 - 50 MHz Channel Link II Serializer/Deserializer with LVDS Parallel Interface Check for Samples: DS92LV0411, DS92LV0412 FEATURES DESCRIPTION • The DS92LV0411 serializer and DS92LV0412

Contextual Info: DS99R105, DS99R106 www.ti.com SNLS242C – MARCH 2007 – REVISED OCTOBER 2007 DS99R105/DS99R106 3-40MHz DC-Balanced 24-Bit LVDS Serializer and Deserializer Check for Samples: DS99R105, DS99R106 FEATURES 1 • 2 • • • • • • • 3 MHz–40 MHz clock embedded and DCBalancing 24:1 and 1:24 data transmissions

Contextual Info: DS99R105,DS99R106 DS99R105/DS99R106 3-40MHz DC-Balanced 24-Bit LVDS Serializer and Deserializer Literature Number: SNLS242C DS99R105/DS99R106 3-40MHz DC-Balanced 24-Bit LVDS Serializer and Deserializer General Description • Internal DC Balancing encode/decode – Supports AC-

DS90C124

Abstract: AEC-Q100 AN-1108 AN-1217 DS90C241 ISO10605 RGB666
Contextual Info: DS90C241/DS90C124 5-35MHz DC-Balanced 24-Bit FPD-Link II Serializer and Deserializer General Description • User selectable clock edge for parallel data on both The DS90C241/DS90C124 Chipset translates a 24-bit parallel bus into a fully transparent data/control LVDS serial stream

RGB666

Abstract: 800X480 DS90C124
Contextual Info: DS90C241/DS90C124 5-35MHz DC-Balanced 24-Bit LVDS Serializer and Deserializer General Description • User selectable clock edge for parallel data on both The DS90C241/124 Chipset translates a 24-bit parallel bus into a fully transparent data/control LVDS serial stream with

960Mbps

Contextual Info: DS99R101/DS99R102 3-40MHz DC-Balanced 24-Bit LVDS Serializer and Deserializer General Description • Internal DC Balancing encode/decode – Supports AC- The DS99R101/102 Chipset translates a 24-bit parallel bus into a fully transparent data/control LVDS serial stream with

Contextual Info: SERDES Evaluation Kit DS90UR241/124 USB Version 0.1 User Manual SERDES Demonstration Kit User Manual Rev 0.2 NSID: SERDESUR-43USB National Semiconductor Corporation Date: 5/8/2008 Page 1 of 36 SERDES Evaluation Kit DS90UR241/124 USB Version 0.1 User Manual

Contextual Info: FPD to Serdes UR Translator Chip DS99R421 Evaluation Kit User’s Manual NSID: FPDXSDUR-43USB Rev 0.0 National Semiconductor Corporation Date: 4/23/2014 Page 1 of 39 Table of Contents TABLE OF CONTENTS . 2

VBC48A

Abstract: DS90C124
Contextual Info: DS90C124,DS90C241 DS90C241/DS90C124 5-35MHz DC-Balanced 24-Bit FPD-Link II Serializer and Deserializer Literature Number: SNLS209K DS90C241/DS90C124 5-35MHz DC-Balanced 24-Bit FPD-Link II Serializer and Deserializer General Description • User selectable clock edge for parallel data on both

Contextual Info: DS99R101 ,DS99R102 DS99R101/DS99R102 3-40MHz DC-Balanced 24-Bit LVDS Serializer and Deserializer T exa s iN S T R U M E N T S Literature Number: SNLS240C Sem iconductor DS99R101 /DS99R102 3-40MHz DC-Balanced 24-Bit LVDS Serializer and Deserializer General Description

DS90UR906

Abstract: BEADS FILTER AEC DS90UR908 AEC-Q100 DS90C124 DS90UR124 DS90UR907Q DS99R124 RGB888
Contextual Info: DS90UR907Q 5 - 65 MHz 24-bit Color FPD-Link to FPD-Link II Converter General Description Features The DS90UR907Q converts FPD-Link to FPD-Link II. It translates four LVDS data/control streams and one LVDS clock pair FPD-Link into a high-speed serialized interface (FPDLink II) over a single pair. This serial bus scheme greatly

DS92LV2412

Contextual Info: DS92LV0411 / DS92LV0412 May 26, 2010 5 - 50 MHz Channel Link II Serializer/Deserializer with LVDS Parallel Interface General Description Features The DS92LV0411 serializer and DS92LV0412 (deserializer) chipset translates a Channel Link LVDS video interface (4

35mhz transmitter circuit

Abstract: PLL VCO 3.5MHz AEC-Q100 AN-1217 ISO10605 RGB666 DS90C241Q
Contextual Info: ご注意：この日本語データシートは参考資料として提供しており内容が最新でない 場合があります。製品のご検討およびご採用に際しては、必ず最新の英文デー タシートをご確認ください。

k2843

Abstract: NC154 74LV128 NC168 NC108 NC143 C495 transistor NC164 NC132 NC130
Contextual Info: ZLAN-57 ZL50211 2048 Channel VEC System Application Note Contents August 2003 The design contained within this document is intended as reference material only, and not as a fully qualified system. It is intended to be used as a starting point for a customer design.

Contextual Info: DS99R101, DS99R102 www.ti.com SNLS240D – MARCH 2007 – REVISED APRIL 2013 DS99R101/DS99R102 3-40MHz DC-Balanced 24-Bit LVDS Serializer and Deserializer Check for Samples: DS99R101, DS99R102 FEATURES 1 • 2 • • • • • • • • • • 3 MHz–40 MHz Clock Embedded and DCBalancing 24:1 and 1:24 Data Transmissions