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    S-PQFP-G32 PCB Search Results

    S-PQFP-G32 PCB Result Highlights (5)

    Part ECAD Model Manufacturer Description Download Buy
    MC68020EH33E Rochester Electronics LLC Rochester Manufactured MC68020, Microprocessor, 132 PQFP Package, Commercial Temp spec. Visit Rochester Electronics LLC Buy
    MC68020EH16E-G Rochester Electronics LLC Rochester Manufactured MC68020, Microprocessor, 132 PQFP Package, Commercial Temp spec. Visit Rochester Electronics LLC Buy
    ZLEDPCB2 Renesas Electronics Corporation LED Test PCBs Visit Renesas Electronics Corporation
    ZLEDPCB10 Renesas Electronics Corporation LED Test PCB - 12x 0.5W Visit Renesas Electronics Corporation
    ZLEDPCB1B Renesas Electronics Corporation LED Test PCB - 3W Visit Renesas Electronics Corporation

    S-PQFP-G32 PCB Datasheets Context Search

    Catalog Datasheet MFG & Type PDF Document Tags

    d151811

    Abstract: 226 20K 340 A23 851 diode ep20k400 esab compact 125 bga 529 EPF20K100 AM2 Processor Functional Data Sheet resistor PC 817 data sheet BGA and QFP Package
    Text: APEX 20K Programmable Logic Device Family November 1999, ver. 2.05 Features. Data Sheet • Preliminary Information ■ Industry’s first programmable logic device PLD incorporating System-on-a-Programmable-ChipTM integration – MultiCoreTM architecture integrating look-up table (LUT) logic,


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    am3 938 pinout

    Abstract: MA 573 U18 524 BN 672 M3
    Text: APEX 20K Programmable Logic Device Family March 2000, ver. 2.06 Data Sheet Features. • Preliminary Information ■ Industry’s first programmable logic device PLD incorporating system-on-a-programmable-chip integration – MultiCoreTM architecture integrating look-up table (LUT) logic,


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    MOSFET P239

    Abstract: XC4000XLA VDR P275 L20 P55 MOSFET XC4000E XC4000X XC4000XL XC4000XV XC4013XLA XC4028XLA
    Text: XC4000XLA/XV Field Programmable Gate Arrays R February 1, 1999 Version 1.0 6* Product Specification XC4000XLA/XV Family FPGAs XC4000XLA/XV Electrical Features Note: XC4000XLA devices are improved versions of XC4000XL devices. The XC4000XV devices have the


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    PDF XC4000XLA/XV XC4000XLA/XV XC4000XLA XC4000XL XC4000XV XC4000E XC4000X MOSFET P239 VDR P275 L20 P55 MOSFET XC4013XLA XC4028XLA

    Axcelerator FPGAs

    Abstract: AX125 AX2000 CQ208 CS180 PQ208 M33 thermal fuse AK 1022 Axcelerator Family FPGAs
    Text: v2 .1  Axcelerator Family FPGAs u e Leading-Edge Performance • • • • – 350+ MHz System Performance 500+ MHz Internal Performance High-Performance Embedded FIFOs 700Mb/s LVDS Capable I/Os Specifications • • • • • Up to 2 Million Equivalent System Gates


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    PDF 700Mb/s 295kbits Axcelerator FPGAs AX125 AX2000 CQ208 CS180 PQ208 M33 thermal fuse AK 1022 Axcelerator Family FPGAs

    896-Pin

    Abstract: smartpower IO290 Axcelerator Family FPGAs
    Text: v2.2 Axcelerator Family FPGAs u e Leading-Edge Performance • • • • – 350+ MHz System Performance 500+ MHz Internal Performance High-Performance Embedded FIFOs 700 Mb/s LVDS Capable I/Os Specifications • • • • • Up to 2 Million Equivalent System Gates


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    MA 6013

    Abstract: No abstract text available
    Text: v2.5 Axcelerator Family FPGAs u e Leading-Edge Performance • • • • – 350+ MHz System Performance 500+ MHz Internal Performance High-Performance Embedded FIFOs 700 Mb/s LVDS Capable I/Os Specifications • • • • • Up to 2 Million Equivalent System Gates


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    ACTEL CCGA 1152 mechanical

    Abstract: AX125 AX2000 CQ208 CQ256 CS180 FG256 PQ208 Trd16 Axcelerator Family FPGAs
    Text: v2.8 Axcelerator Family FPGAs u e Leading-Edge Performance • • • • – 350+ MHz System Performance 500+ MHz Internal Performance High-Performance Embedded FIFOs 700 Mb/s LVDS Capable I/Os Specifications • • • • • Up to 2 Million Equivalent System Gates


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    ACTEL CCGA 1152 mechanical

    Abstract: lga 4x4 footprint AX125 AX2000 CQ208 CS180 FG256 PQ208 624-Pin tx 434
    Text: v2.7 Axcelerator Family FPGAs u e Leading-Edge Performance • • • • – 350+ MHz System Performance 500+ MHz Internal Performance High-Performance Embedded FIFOs 700 Mb/s LVDS Capable I/Os Specifications • • • • • Up to 2 Million Equivalent System Gates


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    GCLR

    Abstract: 676P Axcelerator Family FPGAs
    Text: v2.4 Axcelerator Family FPGAs u e Leading-Edge Performance • • • • – 350+ MHz System Performance 500+ MHz Internal Performance High-Performance Embedded FIFOs 700 Mb/s LVDS Capable I/Os Specifications • • • • • Up to 2 Million Equivalent System Gates


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    AF4 din 74

    Abstract: AF2.5 din 74 diode t25 4 g8 Axcelerator Family FPGAs
    Text: v2.5 Axcelerator Family FPGAs u e Leading-Edge Performance • • • • – 350+ MHz System Performance 500+ MHz Internal Performance High-Performance Embedded FIFOs 700 Mb/s LVDS Capable I/Os Specifications • • • • • Up to 2 Million Equivalent System Gates


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    ACTEL CCGA 1152 mechanical

    Abstract: ACTEL CCGA 624 mechanical L33 thermal fuse ACTEL CCGA 1152 pin configuration actel PLL schematic footprint cqfp 240 m20 thermal fuse 115 M33 thermal fuse AX125 AX2000
    Text: v2.6 Axcelerator Family FPGAs u e Leading-Edge Performance • • • • – 350+ MHz System Performance 500+ MHz Internal Performance High-Performance Embedded FIFOs 700 Mb/s LVDS Capable I/Os Specifications • • • • • Up to 2 Million Equivalent System Gates


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    IO191

    Abstract: Axcelerator Family FPGAs
    Text: v2.3 Axcelerator Family FPGAs u e Leading-Edge Performance • • • • – 350+ MHz System Performance 500+ MHz Internal Performance High-Performance Embedded FIFOs 700 Mb/s LVDS Capable I/Os Specifications • • • • • Up to 2 Million Equivalent System Gates


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    APA300 datasheet

    Abstract: APA600-PQ208M h9 317 APA075 APA1000 APA150 APA300 APA450 APA750 ACTEL proASIC PLUS APA450
    Text: v5.7 ProASICPLUS ® Flash Family FPGAs Features and Benefits High Performance Routing Hierarchy • • • • High Capacity Commercial and Industrial • • • I/O 75,000 to 1 Million System Gates 27 k to 198 kbits of Two-Port SRAM 66 to 712 User I/Os


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    Untitled

    Abstract: No abstract text available
    Text: v5.3 ProASICPLUS ® Flash Family FPGAs Features and Benefits High Performance Routing Hierarchy • • • • High Capacity Commercial and Industrial • • • I/O 75,000 to 1 Million System Gates 27 k to 198 kbits of Two-Port SRAM 66 to 712 User I/Os


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    Am29 Flash Family

    Abstract: No abstract text available
    Text: v5.1 ProASICPLUS ® Flash Family FPGAs Features and Benefits High Performance Routing Hierarchy • • • • High Capacity Commercial and Industrial • • • I/O 75,000 to 1 Million System Gates 27 k to 198 kbits of Two-Port SRAM 66 to 712 User I/Os


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    PDF 32-Bit Am29 Flash Family

    APA1000

    Abstract: actel PLL schematic AD 149 AE9 APA075 APA150 APA300 APA450 APA750 624 CCGA ACTEL proASIC PLUS APA450
    Text: v5.5 ProASICPLUS ® Flash Family FPGAs Features and Benefits High Performance Routing Hierarchy • • • • High Capacity Commercial and Industrial • • • I/O 75,000 to 1 Million System Gates 27 k to 198 kbits of Two-Port SRAM 66 to 712 User I/Os


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    Untitled

    Abstract: No abstract text available
    Text: v5.4 ProASICPLUS ® Flash Family FPGAs Features and Benefits High Performance Routing Hierarchy • • • • High Capacity Commercial and Industrial • • • I/O 75,000 to 1 Million System Gates 27 k to 198 kbits of Two-Port SRAM 66 to 712 User I/Os


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    G1152

    Abstract: RAM256X9SST
    Text: v5.2 ProASICPLUS ® Flash Family FPGAs Features and Benefits High Performance Routing Hierarchy • • • • High Capacity Commercial and Industrial • • • I/O 75,000 to 1 Million System Gates 27 k to 198 kbits of Two-Port SRAM 66 to 712 User I/Os


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    PDF 32-Bit G1152 RAM256X9SST

    DP U1

    Abstract: IO317 AX1000
    Text: Advanced v1.5  Axcelerator Family FPGAs Leading-Edge Performance • • • • – Voltage-Referenced I/O Standards: GTL+, HSTL Class 1, SSTL2 Class 1 and 2, SSTL3 Class 1 and 2 – Registered I/Os with 64-bit Deep FIFO on Each Pin "PerPin FIFO" – Hot-Swap Compliant I/Os (Except PCI)


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    PDF 700Mb/s 339kbits DP U1 IO317 AX1000

    pj 48 diode

    Abstract: BUT16 LD48
    Text: LatticeECP2/M Family Handbook HB1003 Version 05.1, September 2011 LatticeECP2/M Family Handbook Table of Contents September 2011 Section I. LatticeECP2/M Family Data Sheet Introduction Features . 1-1


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    PDF HB1003 TN1105 TN1107 TN1108 TN1109 TN1124 TN1102 TN1104 pj 48 diode BUT16 LD48

    v1493a

    Abstract: AK 1022
    Text: Advanced v1.4  Axcelerator Family FPGAs Leading-Edge Performance • • • • – Voltage-Referenced I/O Standards: GTL+, HSTL Class 1, SSTL2 Class 1 and 2, SSTL3 Class 1 and 2 – Registered I/Os with 64-bit Deep FIFO on Each Pin "PerPin FIFO" – Hot-Swap Compliant I/Os (Except PCI)


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    PDF 700Mb/s 339kbits v1493a AK 1022

    GIGABYTE G41

    Abstract: 82360SL intel 82360SL
    Text: INTEL CORP UP/PRPHLS 3IE D 402tl7S 00aSbb7 2 int@l 7 = V f-/7 -^ 2 386TM SL MICROPROCESSOR SuperSet Highly-Integrated Static 386 Microprocessor Complete ISA Peripheral Subsystem System-Wide Power Management Static 386™ CPU Core — Runs MS-DOS*, WINDOWS*, O S/2*


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    PDF 402tl7S 00aSbb7 386TM 386TM 10-2c. 82360SL 196-Leadâ Ebl75 0125x0 GIGABYTE G41 intel 82360SL

    a8w transistor

    Abstract: 21T-2 1K32
    Text: FLEX 10K Includes F LE X 10KA Embedded Programmable Logic Family May 1999» ver.4 Features. Data Sheet ^ §£ The industry's first em bedded program m able logic device PLD family, providing System -on-a-Program m able-Chip integration Em bedded array for im plem enting m egafunctions, such as


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    PDF EPF10K100A 600-pin a8w transistor 21T-2 1K32

    TI 35X35 BGA 368 BGA

    Abstract: EPF20K
    Text: APEX 20K Programmable Logic Device Family November 1999. ver. 2.05 FeatU r6S D atasheet P re lim in a r y In fo rm a tio n • Industry's first program m able logic device PLD incorporating System -on-a-Program m able-Chip integration M ultiCore™ architecture integrating look-up table (LUT) logic,


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