Untitled
Abstract: No abstract text available
Text: FT61256 L HIGH SPEED 32K x 8 STATIC CMOS RAM FEATURES Fully TTL Compatible Inputs and Outputs Advanced CMOS Technology Fast tOE Automatic Power Down Packages —28-Pin 300 mil DIP, SOJ, TSOP —28-Pin 300 mil Ceramic DIP —28-Pin 600 mil Ceramic DIP —28-Pin CERPACK
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Original
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FT61256
--28-Pin
--32-Pin
144-bit
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PDF
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1519B
Abstract: P4C1256 P4C1256L
Text: P4C1256 HIGH SPEED 32K x 8 STATIC CMOS RAM FEATURES Fully TTL Compatible Inputs and Outputs Advanced CMOS Technology Fast tOE Automatic Power Down Packages —28-Pin 300 mil DIP, SOJ, TSOP —28-Pin 300 mil Ceramic DIP —28-Pin 600 mil Ceramic DIP —28-Pin CERPACK
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Original
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P4C1256
--28-Pin
--32-Pin
P4C1256
loc00
1519B
P4C1256L
|
PDF
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Untitled
Abstract: No abstract text available
Text: FT61256 L HIGH SPEED 32K x 8 STATIC CMOS RAM FEATURES Fully TTL Compatible Inputs and Outputs Advanced CMOS Technology Fast tOE Automatic Power Down Packages —28-Pin 300 mil DIP, SOJ, TSOP —28-Pin 300 mil Ceramic DIP —28-Pin 600 mil Ceramic DIP —28-Pin CERPACK
|
Original
|
FT61256
--28-Pin
--32-Pin
144-bit
|
PDF
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P4C1256L
Abstract: No abstract text available
Text: P4C1256L LOW POWER 32K x 8 STATIC CMOS RAM FEATURES Common Data I/O Three-State Outputs Fully TTL Compatible Inputs and Outputs Advanced CMOS Technology Automatic Power Down Packages —28-Pin 600 mil DIP —28-Pin 300 mil CERDIP —28-Pin 300 mil Narrow Body SOP
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Original
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P4C1256L
--28-Pin
70mA/85mA
P4C1256L
144-bit
32Kx8.
SRAM121
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PDF
|
Untitled
Abstract: No abstract text available
Text: P3C1256L LOW POWER 32K x 8 STATIC CMOS RAM FEATURES VCC Current Commercial/Industrial — Operating: 70mA/85mA — CMOS Standby: 100µA/100µA Access Times —55/70/85 Single 3.3 Volts ± 10% Power Supply Easy Memory Expansion Using CE and OE Inputs Three-State Outputs
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Original
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P3C1256L
70mA/85mA
28-Pin
P3C1256L
144-bit
32Kx8.
SRAM143
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PDF
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P4C1256L
Abstract: No abstract text available
Text: P4C1256L LOW POWER 32K x 8 STATIC CMOS RAM FEATURES VCC Current Commercial/Industrial — Operating: 70mA/85mA — CMOS Standby: 100µA/100µA Access Times —55/70/85 Single 5 Volts ±10% Power Supply Easy Memory Expansion Using CE and OE Inputs Common Data I/O
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Original
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P4C1256L
70mA/85mA
28-Pin
350x550mil)
32-Pin
450x550mil)
P4C1256L
|
PDF
|
P4C1256L
Abstract: No abstract text available
Text: P4C1256L LOW POWER 32K X 8 STATIC CMOS RAM FEATURES VCC Current Commercial/Industrial — Operating: 70mA/85mA — CMOS Standby: 100µA/100µA Access Times —55/70/85 Single 5 Volts ±10% Power Supply Easy Memory Expansion Using CE and OE Inputs Common Data I/O
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Original
|
P4C1256L
70mA/85mA
28-Pin
350x550mil)
32-Pin
450x550mil)
P4C1256L
|
PDF
|
Untitled
Abstract: No abstract text available
Text: P4C1256L LOW POWER 32K X 8 STATIC CMOS RAM FEATURES VCC Current Commercial/Industrial — Operating: 70mA/85mA — CMOS Standby: 100µA/100µA Access Times —55/70/85 Single 5 Volts ±10% Power Supply Easy Memory Expansion Using CE and OE Inputs Common Data I/O
|
Original
|
P4C1256L
70mA/85mA
28-Pin
350x550mil)
32-Pin
450x550mil)
|
PDF
|
Untitled
Abstract: No abstract text available
Text: P3C1256L LOW POWER 32K X 8 STATIC CMOS RAM FEATURES VCC Current Commercial/Industrial — Operating: 70mA/85mA — CMOS Standby: 100µA/100µA Access Times —55/70/85 Wide Range Power Supply: 2.7V to 3.6V Three-State Outputs Fully TTL Compatible Inputs and Outputs
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Original
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P3C1256L
70mA/85mA
28-Pin
P3C1256L
144-bit
32Kx8.
SRAM143
|
PDF
|
P3C1256L
Abstract: No abstract text available
Text: P3C1256L LOW POWER 32K x 8 STATIC CMOS RAM FEATURES VCC Current Commercial/Industrial — Operating: 70mA/85mA — CMOS Standby: 100µA/100µA Access Times —55/70/85 Wide Range Power Supply: 2.7V to 3.6V Easy Memory Expansion Using CE and OE Inputs Three-State Outputs
|
Original
|
P3C1256L
70mA/85mA
28-Pin
P3C1256L
144-bit
32Kx8.
SRAM143
|
PDF
|
Untitled
Abstract: No abstract text available
Text: FT61256 High Speed 32Kx8 Static CMOS Ram FEATURES High Speed Equal Access and Cycle Times – 12/15/20/25/35 ns (Commercial) – 15/20/25/35/45 ns (Industrial) – 20/25/35/45/55/70 ns (Military) Low Power Single 5V±10% Power Supply Easy Memory Expansion Using CE and OE Inputs
|
Original
|
32Kx8
28-Pin
32-Pin
FT61256
|
PDF
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P4C1256
Abstract: P4C1256L
Text: P4C1256 HIGH SPEED 32K x 8 STATIC CMOS RAM FEATURES High Speed Equal Access and Cycle Times – 12/15/20/25/35 ns (Commercial) – 15/20/25/35/45 ns (Industrial) – 20/25/35/45/55/70 ns (Military) Low Power Single 5V±10% Power Supply Easy Memory Expansion Using CE and OE Inputs
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Original
|
P4C1256
28-Pin
32-Pin
P4C1256
P4C1256L
|
PDF
|
Untitled
Abstract: No abstract text available
Text: P4C1256 HIGH SPEED 32K X 8 STATIC CMOS RAM FEATURES High Speed Equal Access and Cycle Times – 12/15/20/25/35 ns (Commercial) – 15/20/25/35/45 ns (Industrial) – 20/25/35/45/55/70 ns (Military) Low Power Single 5V±10% Power Supply Easy Memory Expansion Using CE and OE Inputs
|
Original
|
P4C1256
28-Pin
32-Pin
P4C1256
|
PDF
|
Untitled
Abstract: No abstract text available
Text: P4C1256 HIGH SPEED 32K x 8 STATIC CMOS RAM FEATURES High Speed Equal Access and Cycle Times – 12/15/20/25/35 ns (Commercial) – 15/20/25/35/45 ns (Industrial) – 20/25/35/45/55/70 ns (Military) Low Power Single 5V±10% Power Supply Easy Memory Expansion Using CE and OE Inputs
|
Original
|
P4C1256
28-Pin
32-Pin
P4C1256
144-bit
|
PDF
|
|
|
74LS113
Abstract: No abstract text available
Text: 74LS113, S113 Signetics Flip-Flops Dual J-K Edge-Triggered Flip-Flop Product Specification Logic Products DESCRIPTION The '113 is a dual J-K negative edgetriggered flip-flop featuring individual J, K, Set and Clock inputs. The asynchro nous Set S d input, w hen LOW, forces
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OCR Scan
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74LS113,
1N916,
1N3064,
500ns
500ns
74LS113
|
PDF
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Transistors wmv 02
Abstract: TLE2426 TLV2324 TLV2334 TLV2334ID TLV2334Y TLV2344
Text: TLV2334I, TLV2334Y LinCMOS LOW-VOLTAGE MEDIUM-POWER QUAD OPERATIONAL AMPLIFIERS _ • W id e R ange o f S u p p ly Voltages O ver Specified T em perature Range: T a = - 4 0 ° C to 85°C . . . 2 V to 8 V SLO S113 - MAY 1992
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OCR Scan
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TLV2334I,
TLV2334Y
SLOS113
TLV2344
TLV2324
SLOS113-
Transistors wmv 02
TLE2426
TLV2334
TLV2334ID
|
PDF
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74LS113
Abstract: C0056
Text: 74LS113, S113 Signetics Flip-Flops Dual J-K Edge-Triggered Flip-Flop Product Specification Logic Products DESCRIPTION T h e '1 1 3 is a dual J-K negative edgetriggered flip-flop featuring individual J, K, S e t and Clock inputs. Th e asynchro nous S e t Sq input, w hen LOW , forces
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OCR Scan
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74LS113,
1N916,
1N3064,
500ns
500ns
74LS113
C0056
|
PDF
|
74LS113
Abstract: No abstract text available
Text: 74LS113, S113 Flip-Flops S ig n e tics Dual J-K Edge-Triggered Flip-Flop Product Specification Logic Products DESCRIPTION TYPE T h e '1 1 3 is a dual J-K negative edgetriggered flip-flop featuring individual J, K, S e t and Clock inputs. T h e asynchro nous S et Sp input, when LO W , forces
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OCR Scan
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74LS113,
500ns
500ns
1N916,
1N3064,
74LS113
|
PDF
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74LS113
Abstract: 1N3064 1N916 74LS 74S113 N74LS113N N74S113N S113
Text: 74LS113, S113 Signetics Flip-Flops Dual J-K Edge-Triggered Flip-Flop Product Specification Logic Products DESCRIPTION T h e '1 1 3 is a d u a l J -K n e g a tive edg e trig g e re d flip -flo p fe a tu rin g ind ivid u a l J, K, S e t and C lo c k inp u ts. T h e a s y n c h ro
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OCR Scan
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74LS113,
1N916,
1N3064,
500ns
74LS113
1N3064
1N916
74LS
74S113
N74LS113N
N74S113N
S113
|
PDF
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1N3064
Abstract: 1N916 54S113 54SXXX
Text: 5 4 S113 S ìg n e tic s Flip-Flops Dual J-K Edge-Triggered Flip-Flop Product Specification Military Logic Products ORDERING INFORMATION DESCRIPTION T h e '1 1 3 is a dual J-K n e g a tive edgetrig g e re d flip -flo p fe a tu rin g ind ivid u a l J, K, S e t a n d C lo ck inp u ts. T h e a s y n c h ro
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OCR Scan
|
54S113
54LSXXX
500ns
54XXX
54SXXX
500ns
1N916,
1N3064,
1N3064
1N916
54S113
|
PDF
|
74LS113
Abstract: 1N3064 1N916 74LS 74S113 N74LS113N N74S113N S113
Text: 74LS113, S 'it e Signetics Flip-Flops Dual J-K Edge-Triggered Flip-Flop Product Specification Logic Products DESCRIPTION T h e '1 1 3 is a dual J -K n e g a tive e dg e trig g e re d flip -flo p fe a tu rin g individ u a l J, K, S e t a n d C lo c k inp u ts. T h e a s y n c h ro
|
OCR Scan
|
74LS113,
tr113,
1N916,
1N3064,
500ns
74LS113
1N3064
1N916
74LS
74S113
N74LS113N
N74S113N
S113
|
PDF
|
Untitled
Abstract: No abstract text available
Text: VMS113 VLSI Techn >iogy Data Sheet VLSI Technology V M S 1 1 3 Data Sheet Revision: 2.1 VLSI Technology, Incorporated 2/5/99 Rev. 2.1 VMS113 VLSI ^ T e c h no l og y Data Sheet Revision History Dull1 *hanj»i‘s U e\ision 1/28/99 Baseline Version 2.0 2/5/99
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OCR Scan
|
VMS113
|
PDF
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nec 2761
Abstract: l021 IP276
Text: PRELIMINARY PRODUCT INFORMATION NEC MOS INTEGRATED CIRCUIT ELECTRON DEVICE _ , u P D 1 6 4 2 1 SOURCE DRIVER FOR 120-OUTPUT TFT-LCD CAPABLE OF ACCOMMODATING UP TO 8 TONES The /JPD16421 is a source driver for TFT-LCD and can accommodate up to 8 tones.
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OCR Scan
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120-OUTPUT
uPD16421
12-bit
PD16421
M27S25
PD16421
b45752S
/IPD16421
nec 2761
l021
IP276
|
PDF
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20K potentiometer
Abstract: lt1001 LT1001-ACN8
Text: y n v j x i y n Precision O perational A m p lifie r _ F e a tu r e d " • Guaranteed Low Offset Voltage LT1001AM . 15/uV max LT1001C . 60juV max
|
OCR Scan
|
LT1001
LT1001C
60/uV,
LT1001AM,
15/iV
OP-07
20K potentiometer
LT1001-ACN8
|
PDF
|
