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    SN74LVC32

    Abstract: No abstract text available
    Text: SN74LVC32 QUADRUPLE 2-INPUT POSITIVE-OR GATE SCAS286B – JANUARY 1993 – REVISED JULY 1995 D D D D D D D EPIC  Enhanced-Performance Implanted CMOS Submicron Process ESD Protection Exceeds 2000 V Per Mil-STD-883C, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0)


    Original     		PDF SN74LVC32 SCAS286B Mil-STD-883C, JESD-17 SN74LVC32

    Untitled

    Abstract: No abstract text available
    Text: SN74LVC32 QUADRUPLE 2-INPUT POSITIVE-OR GATE SCAS286B - JANUARY 1993 - REVISED JULY 19SS | D, DB, OR PW PACKAGE TOP VIEW • EPIC (Enhanced-Performance Implanted CMOS) Submicron Process • ESD Protection Exceeds 2000 V Per MII-STD-883C, Method 3015; Exceeds 200 V


    OCR Scan     		PDF SN74LVC32 SCAS286B MII-STD-883C, JESD-17

    Untitled

    Abstract: No abstract text available
    Text: SN74LVC14 HEX SCHMITT-TRIGGER INVERTER SCAS285B - MARCH 1993 - REVISED JULY 1995 • EP/C Enhanced-Performance Implanted CMOS Submicron Process I D, DB, OR PW PACKAGE (TOP VIEW) • ESD Protection Exceeds 2000 V Per MIL-STD-883C, Method 3015; Exceeds


    OCR Scan     		PDF SN74LVC14 SCAS285B MIL-STD-883C, JESD-17