Please enter a valid full or partial manufacturer part number with a minimum of 3 letters or numbers

    SCHEMATIC DIAGRAM UPS 600 ACTEL SILICON SCULPTOR Search Results

    SCHEMATIC DIAGRAM UPS 600 ACTEL SILICON SCULPTOR Result Highlights (5)

    Part ECAD Model Manufacturer Description Download Buy
    MX0912B251Y Rochester Electronics LLC MX0912B251Y - NPN Silicon RF Power Transistor (Ampleon Die) Visit Rochester Electronics LLC Buy
    CA3046 Rochester Electronics LLC RF Small Signal Bipolar Transistor, 0.05A I(C), 5-Element, Very High Frequency Band, Silicon, NPN, MS-001AA, MS-001AA, 14 PIN Visit Rochester Electronics LLC Buy
    DM7490AN Rochester Electronics LLC Decade Counter, TTL/H/L Series, Asynchronous, Negative Edge Triggered, 3-Bit, Up Direction, TTL, PDIP14, 0.300 INCH, PLASTIC, MS-001, DIP-14 Visit Rochester Electronics LLC Buy
    SN74LS490N Rochester Electronics LLC Decade Counter, LS Series, Asynchronous, Negative Edge Triggered, 4-Bit, Up Direction, TTL, PDIP16, PLASTIC, DIP-16 Visit Rochester Electronics LLC Buy
    54LS92J/B Rochester Electronics LLC Divide By 12 Counter, LS Series, Asynchronous, Negative Edge Triggered, 3-Bit, Up Direction, TTL, CDIP14, CERAMIC, DIP-14 Visit Rochester Electronics LLC Buy

    SCHEMATIC DIAGRAM UPS 600 ACTEL SILICON SCULPTOR Datasheets Context Search

    Catalog Datasheet MFG & Type Document Tags PDF

    GL324

    Abstract: ads pa-600 ups 400 ec
    Text: v3.3 TM ProASICPLUS Flash Family FPGAs Fe a t ur es an d B e ne f i ts • 100% Routability and Utilization High C apaci t y I/O • 75,000 to 1 million System Gates • 27k to 198kbits of Two-Port SRAM • 66 to 712 User I/Os Rep ro gra m m able Fl as h T ech nol ogy


    Original
    198kbits GL324 ads pa-600 ups 400 ec PDF

    RAM256X9SST

    Abstract: ProASIC PLUS v0.1
    Text: Advanced v0.6 ProASICPLUS Family Flash FPGAs Fe a t ur es an d B e ne f i ts I/O High C apaci t y • Schmitt Trigger option on Every Input • Mixed 2.5V/3.3V Support with Individually-Selectable Voltage and Slew Rate • Bidirectional Global I/Os • Compliance with PCI Specification Revision 2.2


    Original
    32-bit RAM256X9SST ProASIC PLUS v0.1 PDF

    rdl 117-a

    Abstract: pa-1000b
    Text: A d v a n c e d v O .7 ? TM P r o A S IC ^ F la s h F a m ily F P G A s High Performance, Low Skew, Splitable Global Network 100% Routability and Utilization I/O Schmitt-Trigger Option on Every Input Mixed 2.5V/3.3V Support with Individually-Selectable Voltage and Slew Rate


    OCR Scan
    198kbits rdl 117-a pa-1000b PDF