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    SDRAM PINS DETAIL Search Results

    SDRAM PINS DETAIL Result Highlights (5)

    Part ECAD Model Manufacturer Description Download Buy
    CS-DSDMDB09MF-010 Amphenol Cables on Demand Amphenol CS-DSDMDB09MF-010 9-Pin (DB9) Deluxe D-Sub Cable - Copper Shielded - Male / Female 10ft Datasheet
    CS-DSDMDB15MF-002.5 Amphenol Cables on Demand Amphenol CS-DSDMDB15MF-002.5 15-Pin (DB15) Deluxe D-Sub Cable - Copper Shielded - Male / Female 2.5ft Datasheet
    CS-DSDMDB15MM-025 Amphenol Cables on Demand Amphenol CS-DSDMDB15MM-025 15-Pin (DB15) Deluxe D-Sub Cable - Copper Shielded - Male / Male 25ft Datasheet
    CS-DSDMDB25MM-010 Amphenol Cables on Demand Amphenol CS-DSDMDB25MM-010 25-Pin (DB25) Deluxe D-Sub Cable - Copper Shielded - Male / Male 10ft Datasheet
    CS-DSDMDB37MM-002.5 Amphenol Cables on Demand Amphenol CS-DSDMDB37MM-002.5 37-Pin (DB37) Deluxe D-Sub Cable - Copper Shielded - Male / Male 2.5ft Datasheet

    SDRAM PINS DETAIL Datasheets Context Search

    Catalog Datasheet MFG & Type PDF Document Tags

    Untitled

    Abstract: No abstract text available
    Text: DDR3 SDRAM-DIMM socket 240pins DMM12 Series OUTLINE DMM12 series is DDR3 SDRAM-DIMM socket of 240 pins. FEATURES １．Anti-deflection ・By adjusting the expansion rate of mounting board and resin of connector housing, it has superior mountability and deforming connector housing are a little.


    Original     		PDF 240pins DMM12 G-503606 48Padsï DMM12-S240FA-1N

    W9832AASA

    Abstract: W986416AH ram 32mb
    Text: W9832AASA 32MB 4M x 64 SDRAM SO-DIMM MODULE Features • • • • • • • • • • • JEDEC standard 144 pins, small-outline, dual in-line memory module (SODIMM) Utilizes 100 MHz SDRAM components Unbuffered SO-DIMM Auto Refresh and Self Refresh


    Original     		PDF W9832AASA W9832AASA-10 W9832AASA10L W9832AASA 4Mx16 W986416AH ram 32mb

    W986416AH

    Abstract: W9864AASA
    Text: W9864AASA 64MB 8M x 64 SDRAM SO-DIMM MODULE Features • • • • • • • • • • • • JEDEC standard 144 pins, small-outline, dual in-line memory module (SODIMM) Two memory rows on this module (Double Bank Module) Utilizes 100 MHz SDRAM components


    Original     		PDF W9864AASA cycles/64ms W9864AASA-10 W9864AASA10L W9864AASA 4Mx16 W986416AH

    W986416AH

    Abstract: W9864AADA
    Text: W9864AADA 64MB 8M x 64 PC100 SDRAM MODULE Features • • • • • • • • • • • Intel PC SDRAM compalint 168 pins, dual in-line memory module (DIMM) Two memory rows on this module (Double Bank Module) Unbuffered DIMM Auto Refresh and Self Refresh


    Original     		PDF W9864AADA PC100 cycles/64ms W9864AADA-8H W9864AADA-8N W9864AADA-10 W9864AADA W986416AH

    W9828BADA

    Abstract: W986408AH
    Text: W9828BADA 128MB 16M x 64 PC100 SDRAM MODULE Features • • • • • • • • • • • Intel PC SDRAM compalint 168 pins, dual in-line memory module (DIMM) Two memory rows on this module (Double Bank Module) Unbuffered DIMM Auto Refresh and Self Refresh


    Original     		PDF W9828BADA 128MB PC100 cycles/64ms W9828BADA-8H W9828BADA-8N W9828BADA-10 W9828BADA W986408AH

    W986416AH

    Abstract: W9832AADA
    Text: W9832AADA 32MB 4M x 64 PC100 SDRAM MODULE Features • • • • • • • • • • Intel PC SDRAM compalint 168 pins, dual in-line memory module (DIMM) Unbuffered DIMM Auto Refresh and Self Refresh CAS latency: 2 and 3 Burst Length: 1, 2, 4, 8 and full page


    Original     		PDF W9832AADA PC100 cycles/64ms W9832AADA-8H W9832AADA-8N W9832AADA-10 W9832AADA W986416AH W986416AH

    W986408AH

    Abstract: W9864BADA
    Text: W9864BADA 64MB 8M x 64 PC100 SDRAM MODULE Features • • • • • • • • • • Intel PC SDRAM compalint 168 pins, dual in-line memory module (DIMM) Unbuffered DIMM Auto Refresh and Self Refresh CAS latency: 2 and 3 Burst Length: 1, 2, 4, 8 and full page


    Original     		PDF W9864BADA PC100 cycles/64ms W9864BADA-8H W9864BADA-8N W9864BADA-10 W9864BADA W986408AH W986408AH

    EM47EM3288SBA

    Abstract: No abstract text available
    Text: EM47EM3288SBA Revision History Revision 0.1 May. 2012 -First release. Revision 0.2 (Feb. 2013) -Update ZQ pins description. Revision 0.3 (Apr. 2014) -Update tFAW. Apr. 2014 1/39 www.eorex.com EM47EM3288SBA 8Gb (32Mx8Bank×32) Double DATA RATE 3 Stack SDRAM


    Original     		PDF EM47EM3288SBA 12x14x1 136Ball-FBGA 5x14x1 EM47EM3288SBA

    74 HTC 00

    Abstract: dt1x CRYSTAL14 "32-Bit Microprocessors" DESIGN AND IMPLEMENTATION 16-BIT BARREL SHIFTER ADSP21000 ADSP-21000 ADSP-21060 ADSP-21062 ADSP-21065L
    Text: a DSP Microcomputer ADSP-21065L SDRAM Controller for Glueless Interface to Low Cost External Memory @ 60 MHz 64M Words External Address Range 12 Programmable I/O Pins and 2 Timers with Event Capture Options Code-Compatible with ADSP-2106x Family 208-Lead MQFP Package


    Original     		PDF ADSP-21065L ADSP-2106x 208-Lead 32-Bit 40-Bit Transmit41 ADSP-21065LKS-240 74 HTC 00 dt1x CRYSTAL14 "32-Bit Microprocessors" DESIGN AND IMPLEMENTATION 16-BIT BARREL SHIFTER ADSP21000 ADSP-21000 ADSP-21060 ADSP-21062 ADSP-21065L

    ADSP-21000

    Abstract: ADSP-21060 ADSP-21062 ADSP-21065L 74 HTC 164
    Text: a DSP Microcomputer ADSP-21065L SDRAM Controller for Glueless Interface to Low Cost External Memory @ 66 MHz 64M Words External Address Range 12 Programmable I/O Pins and Two Timers with Event Capture Options Code-Compatible with ADSP-2106x Family 208-Lead MQFP or 196-Ball Mini-BGA Package


    Original     		PDF ADSP-21065L ADSP-2106x 208-Lead 196-Ball 32-Bit 40-Bit MS-034AAE-1. ADSP-21000 ADSP-21060 ADSP-21062 ADSP-21065L 74 HTC 164

    ADSP-21065L

    Abstract: ADSP-21000 ADSP-21060 ADSP-21062
    Text: a DSP Microcomputer ADSP-21065L SDRAM Controller for Glueless Interface to Low Cost External Memory @ 66 MHz 64M Words External Address Range 12 Programmable I/O Pins and Two Timers with Event Capture Options Code-Compatible with ADSP-2106x Family 208-Lead MQFP or 196-Ball Mini-BGA Package


    Original     		PDF ADSP-21065L ADSP-2106x 208-Lead 196-Ball 32-Bit 40-Bit MS-034AAE-1. ADSP-21065L ADSP-21000 ADSP-21060 ADSP-21062

    DT1X

    Abstract: ADSP-21065LKCA-240 ADSP21000 ADSP-21000 ADSP-21060 ADSP-21062 ADSP-21065L 74 HTC 00 ADSP-21065LCS-240
    Text: a DSP Microcomputer ADSP-21065L SDRAM Controller for Glueless Interface to Low Cost External Memory @ 66 MHz 64M Words External Address Range 12 Programmable I/O Pins and Two Timers with Event Capture Options Code-Compatible with ADSP-2106x Family 208-Lead MQFP or 196-Ball Mini-BGA Package


    Original     		PDF ADSP-21065L ADSP-2106x 208-Lead 196-Ball 32-Bit 40-Bit DT1X ADSP-21065LKCA-240 ADSP21000 ADSP-21000 ADSP-21060 ADSP-21062 ADSP-21065L 74 HTC 00 ADSP-21065LCS-240

    ADSP21000

    Abstract: ADSP-21000 ADSP-21060 ADSP-21062 ADSP-21065L DSP-66 TRD-G
    Text: a DSP Microcomputer ADSP-21065L SDRAM Controller for Glueless Interface to Low Cost External Memory @ 66 MHz 64M Words External Address Range 12 Programmable I/O Pins and Two Timers with Event Capture Options Code-Compatible with ADSP-2106x Family 208-Lead MQFP or 196-Ball Mini-BGA Package


    Original     		PDF ADSP-21065L ADSP-2106x 208-Lead 196-Ball 32-Bit 40-Bit ADSP21000 ADSP-21000 ADSP-21060 ADSP-21062 ADSP-21065L DSP-66 TRD-G

    DYNAMIC RAM CROSS REFERENCE

    Abstract: VG37648041AT
    Text: VIS Preliminary VG37648041AT 256M:x4, x8, x16 CMOS Synchronous Dynamic RAM Description The 256Mb DDR SDRAM is a high-speed COMS, dynamic random-access memory containing 268,435,456 bits. It is internally configured as a quad-bank DRAM. The 256Mb DDR SDRAM uses a double-data-rate architecture to achieve high-speed operation. The double data rate architecture is essentially a 2n prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write


    Original     		PDF VG37648041AT 256Mb 1G5-0157 DYNAMIC RAM CROSS REFERENCE VG37648041AT

    Untitled

    Abstract: No abstract text available
    Text: CBTU4411 11-bit DDR2 SDRAM MUX/bus switch with 12 Ω ON resistance Rev. 4 — 18 June 2012 Product data sheet 1. General description This 11-bit bus switch is designed for 1.7 V to 1.9 V VDD operation and SSTL_18 select input levels. Each Host port pin HPn is multiplexed to one of four DIMM port pins (xDPn). The


    Original     		PDF CBTU4411 11-bit

    CBTU4411EE

    Abstract: HP10 JESD22-A114 JESD22-A115 JESD78 001A 2dp1
    Text: CBTU4411 11-bit DDR2 SDRAM MUX/bus switch with 12 Ω ON resistance Rev. 03 — 12 October 2009 Product data sheet 1. General description This 11-bit bus switch is designed for 1.7 V to 1.9 V VDD operation and SSTL_18 select input levels. Each Host port pin HPn is multiplexed to one of four DIMM port pins (xDPn). The


    Original     		PDF CBTU4411 11-bit CBTU4411 CBTU4411EE HP10 JESD22-A114 JESD22-A115 JESD78 001A 2dp1

    Untitled

    Abstract: No abstract text available
    Text: 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 EM47EM3288SBA Revision History Revision 0.1 May. 2012 -First release. Revision 0.2 (Feb. 2013) -Update ZQ pins description. May. 2012 1/38 www.eorex.com 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 EM47EM3288SBA 8Gb (32Mx8Bank×32) Double DATA RATE 3 Stack SDRAM


    Original     		PDF EM47EM3288SBA 136Ball-FBGA

    Untitled

    Abstract: No abstract text available
    Text: CBTU4411 11-bit DDR2 SDRAM MUX/bus switch with 12 Ω ON resistance Rev. 4 — 18 June 2012 Product data sheet 1. General description This 11-bit bus switch is designed for 1.7 V to 1.9 V VDD operation and SSTL_18 select input levels. Each Host port pin HPn is multiplexed to one of four DIMM port pins (xDPn). The


    Original     		PDF CBTU4411 11-bit

    AN328

    Abstract: AP1910 MT47H64M16BT-37E MT47H32M16CC-3 AL1510 EP2SGX90FF1508C3 AL15-10 MT47H64M8CB-3 MT47H64M16 MT47H64M16BT-37E eye
    Text: AN 328: Interfacing DDR2 SDRAM with Stratix II, Stratix II GX, and Arria GX Devices October 2009 AN-328-6.0 Introduction This application note provides information about interfacing DDR2 SDRAM with Stratix II, Stratix II GX, and Arria ® GX devices. It includes details about supported modes and


    Original     		PDF AN-328-6 AN328 AP1910 MT47H64M16BT-37E MT47H32M16CC-3 AL1510 EP2SGX90FF1508C3 AL15-10 MT47H64M8CB-3 MT47H64M16 MT47H64M16BT-37E eye

    DDR2 layout

    Abstract: SSTL-18 SDR SDRAM Controller White Paper SIGNAL PATH DESIGNER
    Text: White Paper Benefits of Altera’s High-Speed DDR2 SDRAM Memory Interface Solution Introduction This white paper provides a general overview of the Double Data Rate 2 DDR2 SDRAM interface, discusses some of the design challenges in DDR2 SDRAM, and details Altera’s solution used to implement


    Original     		PDF

    EP2S90F1020C3

    Abstract: DDR2 layout guidelines sdram controller B34F
    Text: Implementing Multiple Legacy DDR/DDR2 SDRAM Controller Interfaces Application Note 392 July 2007, v2.0 Introduction f This application note details the steps for designing multiple legacy DDR2 controllers into a single FPGA. After reading this application note


    Original     		PDF

    tri state

    Abstract: 82439TX MA13
    Text: 82439TX System Controller MTXC 32.0 Signal Description This section provides a detailed description of each signal. The signals are arranged in functional groups according to their associated interface. The “#” symbol at the end of a signal name indicates that the active, or asserted state occurs when


    Original     		PDF 82439TX tri state MA13

    W48S68

    Abstract: No abstract text available
    Text: ill# ICW 0RKS W48S68-01 4 DIMM Desktop System Clock Features • Generates system clocks for 2.5/3.3V based designs: Separate supply pins for CPU and IOAPIC output buffers: 5 CPU Clocks with 2.5V output swing 16 SDRAM clocks; supports up to four 168 pin DIMM


    OCR Scan     		PDF W48S68-01 318MHz 56-pin W48S68

    Untitled

    Abstract: No abstract text available
    Text: ANALOG DEVICES DSP Microcomputer ADSP-21065L SDRAM Controller for Glueless Interface to Low Cost External M em ory @ 66 MHz 64M Words External Address Range 12 Programmable I/O Pins and T w o Timers w ith Event Capture Options Code-Com patible w ith ADSP-2106x Family


    OCR Scan     		PDF ADSP-21065L ADSP-2106x 208-Lead 196-Ball 32-Bit 40-Bit