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    SERIAL LINK CLOCK SIGNAL Search Results

    SERIAL LINK CLOCK SIGNAL Result Highlights (5)

    Part ECAD Model Manufacturer Description Download Buy
    TB67S539FTG Toshiba Electronic Devices & Storage Corporation Stepping Motor Driver/Bipolar Type/Vout(V)=40/Iout(A)=2/Clock Interface Visit Toshiba Electronic Devices & Storage Corporation
    TB67S149AFTG Toshiba Electronic Devices & Storage Corporation Stepping Motor Driver/Unipolar Type/Vout(V)=84/Iout(A)=3/Clock Interface Visit Toshiba Electronic Devices & Storage Corporation
    TB67S549FTG Toshiba Electronic Devices & Storage Corporation Stepping Motor Driver/Bipolar Type/Vout(V)=40/Iout(A)=1.5/Clock Interface Visit Toshiba Electronic Devices & Storage Corporation
    TB67S589FTG Toshiba Electronic Devices & Storage Corporation Stepping Motor Driver / Bipolar Type / Vout(V)=50 / Iout(A)=3.0 / CLK input type / VQFN32 Visit Toshiba Electronic Devices & Storage Corporation
    TB67S589FNG Toshiba Electronic Devices & Storage Corporation Stepping Motor Driver / Bipolar Type / Vout(V)=50 / Iout(A)=3.0 / CLK input type / HTSSOP28 Visit Toshiba Electronic Devices & Storage Corporation

    SERIAL LINK CLOCK SIGNAL Datasheets Context Search

    Catalog Datasheet MFG & Type PDF Document Tags

    DS90UR421

    Abstract: DS99R124Q AEC-Q100 DS90UR241 DS99R421 RGB666 ISO106
    Text: DS99R124Q 5 - 43 MHz 18-bit Color FPD-Link II to FPD-Link Converter General Description Features The DS99R124Q converts FPD-Link II to FPD-Link. It translates a high-speed serialized interface with an embedded clock over a single pair FPD-Link II to three LVDS data/control streams and one LVDS clock pair (FPD-Link). This serial


    Original     		PDF DS99R124Q 18-bit DS99R124Q DS90UR421 AEC-Q100 DS90UR241 DS99R421 RGB666 ISO106

    BEADS FILTER AEC

    Abstract: DS90UR421 AEC-Q100 DS90UR241 DS99R421 RGB666
    Text: DS99R124AQ 5 - 43 MHz 18-bit Color FPD-Link II to FPD-Link Converter General Description Features The DS99R124AQ converts FPD-Link II to FPD-Link. It translates a high-speed serialized interface with an embedded clock over a single pair FPD-Link II to three LVDS data/control streams and one LVDS clock pair (FPD-Link). This serial


    Original     		PDF DS99R124AQ 18-bit DS99R124AQ BEADS FILTER AEC DS90UR421 AEC-Q100 DS90UR241 DS99R421 RGB666

    AEC-Q100

    Abstract: DS90UR241 DS99R124Q DS99R421 RGB666 DS90UR421
    Text: DS99R124Q 5 - 43 MHz 18-bit Color FPD-Link II to FPD-Link Converter General Description Features The DS99R124Q converts FPD-Link II to FPD-Link. It translates a high-speed serialized interface with an embedded clock over a single pair FPD-Link II to three LVDS data/control streams and one LVDS clock pair (FPD-Link). This serial


    Original     		PDF DS99R124Q 18-bit DS99R124Q AEC-Q100 DS90UR241 DS99R421 RGB666 DS90UR421

    DS90UR124

    Abstract: AEC-Q100 DS90C124 DS90C365A DS90UR241 DS99R421 ISO10605 RGB666 300113
    Text: DS99R421 5-43 MHz FPD-Link LVDS 3 Data + 1 Clock to FPD-Link II LVDS (Embedded Clock DC-Balanced) Converter General Description Features The DS99R421 converts a FPD-Link input with 4 non-DC Balanced LVDS (3 LVDS Data + LVDS Clock) plus 3 oversampled low speed control bits into a single LVDS DC-balanced serial stream with embedded clock information. This


    Original     		PDF DS99R421 DS99R421 24-bit DS90UR124 AEC-Q100 DS90C124 DS90C365A DS90UR241 ISO10605 RGB666 300113

    S2044

    Abstract: D10-19 S2045
    Text: PRELIMINARY DEVICE SPECIFICATION S2044/S2045 S2044/S2045 GLM COMPLIANT SERIAL INTERFACE CIRCUITS GLM COMPLIANT SERIAL INTERFACE CIRCUITS BiCMOS PECL CLOCK GENERATOR FEATURES GENERAL DESCRIPTION • Complies with the electrical and link levels of the Gigabaud Link Module GLM specification


    Original     		PDF S2044/S2045 X3T11 S2044 S2045 20-bit D10-19

    LM4310

    Abstract: LVDS bridge 18bit "18-bit parallel RGB" rgb 18 bit to lvds AN-1187 LM4312 RGB24
    Text: LM4310 Mobile Pixel Link Two MPL-2 , RGB Display Differential Interface Deserializer General Description Features The LM4310 deserializes a Two Data + Clock Mobile Pixel Link (MPL-2) RGB serial link. Two operating modes are supported: 24-bit RGB and also 18-bit RGB.


    Original     		PDF LM4310 LM4310 24-bit 18-bit LM4312 LVDS bridge 18bit "18-bit parallel RGB" rgb 18 bit to lvds AN-1187 RGB24

    laser LED

    Abstract: 680R ACS4005 ACS4050 ACS9010 TQFP44 1M preset potentiometer 3pin package
    Text: ACS9010 Main Features Half duplex serial transmission. * Full duplex serial transmission in Ping Pong systems. * Up to 34Mbps, E3 data rates. * Link lengths up to 25Km for full duplex ping pong . * Link lengths up to 100Km for half duplex. * Switchable PLL Clock Recovery and Data Re-Synchronisation.


    Original     		PDF ACS9010 34Mbps, 100Km ACS4005 laser LED 680R ACS4050 TQFP44 1M preset potentiometer 3pin package

    DS90UR906

    Abstract: BEADS FILTER AEC DS90UR908 AEC-Q100 DS90C124 DS90UR124 DS90UR907Q DS99R124 RGB888
    Text: DS90UR907Q 5 - 65 MHz 24-bit Color FPD-Link to FPD-Link II Converter General Description Features The DS90UR907Q converts FPD-Link to FPD-Link II. It translates four LVDS data/control streams and one LVDS clock pair FPD-Link into a high-speed serialized interface (FPDLink II) over a single pair. This serial bus scheme greatly


    Original     		PDF DS90UR907Q 24-bit DS90UR907Q DS90UR906 BEADS FILTER AEC DS90UR908 AEC-Q100 DS90C124 DS90UR124 DS99R124 RGB888

    DS90UR906

    Abstract: DS99R124Q
    Text: DS90UR907Q 5 - 65 MHz 24-bit Color FPD-Link to FPD-Link II Converter General Description Features The DS90UR907Q converts FPD-Link to FPD-Link II. It translates four LVDS data/control streams and one LVDS clock pair FPD-Link into a high-speed serialized interface (FPDLink II) over a single pair. This serial bus scheme greatly


    Original     		PDF DS90UR907Q 24-bit DS90UR906 DS99R124Q

    AEC-Q100

    Abstract: DS90C124 DS90C365A DS90UR124 DS90UR241 DS99R421 ISO10605 RGB666
    Text: DS99R421 5-43 MHz FPD-Link LVDS 3 Data + 1 Clock to Single Embedded Clock DC-Balanced LVDS Converter General Description Features The DS99R421 converts a FPD-Link input with 4 non-DC Balanced LVDS (3 LVDS Data + LVDS Clock) plus 3 oversampled low speed control bits into a single LVDS DC-balanced serial stream with embedded clock information. This


    Original     		PDF DS99R421 DS99R421 24-bit AEC-Q100 DS90C124 DS90C365A DS90UR124 DS90UR241 ISO10605 RGB666

    40 pin lvds converter

    Abstract: AEC-Q100 DS90C124 DS90C365A DS90UR124 DS90UR241 DS99R421 ISO10605 RGB666 LVDS SERIALIZER SWITCHING NOISE SUPPRESSION
    Text: DS99R421 5-43 MHz FPD-Link LVDS 3 Data + 1 Clock to Single Embedded Clock DC-Balanced LVDS Converter General Description Features The DS99R421 converts a FPD-Link input with 4 non-DC Balanced LVDS (3 LVDS Data + LVDS Clock) plus 3 oversampled low speed control bits into a single LVDS DC-balanced serial stream with embedded clock information. This


    Original     		PDF DS99R421 DS99R421 24-bit 40 pin lvds converter AEC-Q100 DS90C124 DS90C365A DS90UR124 DS90UR241 ISO10605 RGB666 LVDS SERIALIZER SWITCHING NOISE SUPPRESSION

    LVDS Cable STP

    Abstract: AEC-Q100 DS90C124 DS90C365A DS90UR124 DS90UR241 DS99R421 ISO10605 RGB666
    Text: DS99R421 5-43 MHz FPD-Link LVDS 3 Data + 1 Clock to Single Embedded Clock DC-Balanced LVDS Converter General Description Features The DS99R421 converts a FPD-Link input with 4 non-DC Balanced LVDS (3 LVDS Data + LVDS Clock) plus 3 oversampled low speed control bits into a single LVDS DC-balanced serial stream with embedded clock information. This


    Original     		PDF DS99R421 DS99R421 24-bit LVDS Cable STP AEC-Q100 DS90C124 DS90C365A DS90UR124 DS90UR241 ISO10605 RGB666

    LVDS to rgb888

    Abstract: Ferrite Beads AEC DS90UR907Q DS90UR908 FPD-link receiver chip DS90UR906 AEC-Q100 DS90C124 DS90UR124 DS99R124
    Text: DS90UR907Q April 15, 2010 5 - 65 MHz 24-bit Color FPD-Link to FPD-Link II Converter General Description Features The DS90UR907Q converts FPD-Link to FPD-Link II. It translates four LVDS data/control streams and one LVDS clock pair FPD-Link into a high-speed serialized interface (FPDLink II) over a single pair. This serial bus scheme greatly


    Original     		PDF DS90UR907Q 24-bit DS90UR907Q LVDS to rgb888 Ferrite Beads AEC DS90UR908 FPD-link receiver chip DS90UR906 AEC-Q100 DS90C124 DS90UR124 DS99R124

    YAGEO CHIP RESISTORS instruction

    Abstract: AD9287
    Text: Preliminary Technical Data Quad 12-bit, 40/65 MSPS Serial LVDS 1.8 V A/D Converter AD9228 FEATURES FUNCTIONAL BLOCK DIAGRAM Four ADCs in one package Serial LVDS ANSI-644 ,IEEE 1596.3 reduced range link Data and frame clock outputs SNR = 70 dB (to Nyquist)


    Original     		PDF ANSI-644 12-bit, AD9228 MO-220-VKKD-2 48-Lead CP-48-1) AD9228BCPZ-40 AD9228BCPZ-65 AD9228-65EB CP-48 YAGEO CHIP RESISTORS instruction AD9287

    Untitled

    Abstract: No abstract text available
    Text: CYV15G0104TRB PRELIMINARY Independent Clock HOTLink II Serializer and Reclocking Deserializer Features including SMPTE 292M and SMPTE 259M video applications. It supports signaling rates in the range of 195 to 1500 Mbps per serial link. The transmit and receive channels are


    Original     		PDF CYV15G0104TRB 1500-Mbps CYV15G0104TRB

    CYV15G0104TRB

    Abstract: CYV15G0104TRB-BGC smpte 292M hd-SDI deserializer
    Text: CYV15G0104TRB PRELIMINARY Independent Clock HOTLink II Serializer and Reclocking Deserializer Features including SMPTE 292M and SMPTE 259M video applications. It supports signaling rates in the range of 195 to 1500 Mbps per serial link. The transmit and receive channels are


    Original     		PDF CYV15G0104TRB 10-bit 10-bit CYV15G0104TRB CYV15G0104TRB-BGC smpte 292M hd-SDI deserializer

    VCXO 5x7 3.3v

    Abstract: CDCE421 prescalar selection guide
    Text: 10.9MHz–1175MHz Low Phase Noise Clock Evaluation Board User's Guide March 2007 Serial Link Products SCAU020 2 SCAU020 – March 2007 Submit Documentation Feedback Contents 1 2 3 4 5 6 7 8 General Description. 5


    Original     		PDF 1175MHz SCAU020 VCXO 5x7 3.3v CDCE421 prescalar selection guide

    vhdl code for clock and data recovery

    Abstract: vhdl code for PLL manchester code differential manchester encoder differential manchester system design using pll vhdl code "differential manchester" vhdl code manchester encoder manchester verilog decoder vhdl code for manchester decoder
    Text: Control Link Serial Interface November 2010 Reference Design RD1051 Introduction In today’s highly-integrated systems, noise reduction is a high priority for circuit board designers. Serially transmitted data with an embedded clock allows a significant reduction in data traces and eliminates the need to run a clock


    Original     		PDF RD1051 1-800-LATTICE vhdl code for clock and data recovery vhdl code for PLL manchester code differential manchester encoder differential manchester system design using pll vhdl code "differential manchester" vhdl code manchester encoder manchester verilog decoder vhdl code for manchester decoder

    nrzi Decoder

    Abstract: DS32EL0124 DS32EL0124SQ DS32EL0124SQE DS32EL0124SQX DS32ELX0124 DS32ELX0124SQ
    Text: DS32EL0124, DS32ELX0124 125 MHz - 312.5 MHz FPGA-Link Deserializer with DDR LVDS Parallel Interface General Description Features The DS32EL0124/DS32ELX0124 integrates clock and data recovery modules for high-speed serial communication over FR-4 printed circuit board backplanes, balanced cables, and


    Original     		PDF DS32EL0124, DS32ELX0124 DS32EL0124/DS32ELX0124 DS32EL0124/DS32ELX01214 nrzi Decoder DS32EL0124 DS32EL0124SQ DS32EL0124SQE DS32EL0124SQX DS32ELX0124 DS32ELX0124SQ

    DS32ELX0124SQE

    Abstract: DS32EL0124 dvi-d 24 pin diagram DS32EL0124SQ DS32EL0124SQE DS32EL0124SQX DS32ELX0124 DS32ELX0124SQ
    Text: DS32EL0124, DS32ELX0124 125 MHz — 312.5 MHz FPGA-Link Deserializer with DDR LVDS Parallel Interface General Description Features The DS32EL0124/DS32ELX0124 integrates clock and data recovery modules for high-speed serial communication over FR-4 printed circuit board backplanes, balanced cables, and


    Original     		PDF DS32EL0124, DS32ELX0124 DS32EL0124/DS32ELX0124 DS32EL0124/DS32ELX01214 DS32ELX0124SQE DS32EL0124 dvi-d 24 pin diagram DS32EL0124SQ DS32EL0124SQE DS32EL0124SQX DS32ELX0124 DS32ELX0124SQ

    CY7B952

    Abstract: G958 PM5343 WAC013
    Text: CY7B952 SST SONET/SDH Serial Transceiver Features • 100K ECL compatible I/O • OC-3 Compliant with Bellcore and CCITT ITU specifications on: • No output clock “drift” without data transitions • Link Status Indication — Jitter Generation (<0.01 UI)


    Original     		PDF CY7B952 24-pin WAC013, WAC413, PM5343 52-MHz 52-MHz CY7B952 G958 PM5343 WAC013

    CY7B952

    Abstract: G958 PM5343 WAC013
    Text: CY7B952 SST SONET/SDH Serial Transceiver Features • 100K ECL compatible I/O • OC-3 Compliant with Bellcore and CCITT ITU specifications on: • No output clock “drift” without data transitions • Link Status Indication — Jitter Generation (<0.01 UI)


    Original     		PDF CY7B952 24-pin WAC013, WAC413, PM5343 52-MHz 52-MHz CY7B952 G958 PM5343 WAC013

    Untitled

    Abstract: No abstract text available
    Text: fax id: 5009 W CYPRESS PRELIMINARY CY7B952 SST SONET/SDH Serial Transceiver Features No output clock “drift” without data transitions Link Status Indication Fully compliant with Bellcore and CCITT ITU specifi­ cations on: — Jitter Generation (<0.01 Ul)


    OCR Scan     		PDF CY7B952 24-pin PM5343 52-MHz 52-MHz

    Untitled

    Abstract: No abstract text available
    Text: fax id: 5009 PRELIMINARY CYPRESS CY7B952 SST SONET/SDH Serial Transceiver Features No output clock “drift” without data transitions Link Status Indication Fully compliant with Bellcore and CCITT ITU specifi­ cations on: — Jitter Generation (<0.01 Ul)


    OCR Scan     		PDF CY7B952 24-pin PM5343 52-MHz 52-MHz