Untitled
Abstract: No abstract text available
Text: SM57202807UB6AU June 8, 2000 Revision History • June 8, 2000 Added Command Truth Table, Mode Register Table and notes. Modified waveforms Auto Refresh (CBR cycle and Power Down Mode and Clock Mask). • March 19, 1998 Datasheet released. Corporate Headquarters: P. O. Box 1757, Fremont, CA 94538, USA • Tel:(510) 623-1231 • Fax:(510) 623-1434 • E-mail: info@smartm.com
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SM57202807UB6AU
16MByte
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PDF
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SG5723285D8D6CL
Abstract: No abstract text available
Text: SU5723285D8D6CL July 26, 2007 Ordering Information Part Numbers Description Module Speed SM5723285D8D6CL 32Mx72 256MB , DDR, 184-pin DIMM, Unbuffered, ECC, 32Mx8 Based, DDR333B, 31.75mm, 22Ω DQ termination. PC2700 @ CL 2.5 SG5723285D8D6CL 32Mx72 (256MB), DDR, 184-pin DIMM, Unbuffered, ECC,
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SU5723285D8D6CL
SM5723285D8D6CL
SG5723285D8D6CL
32Mx72
256MB)
184-pin
32Mx8
DDR333B,
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PDF
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Untitled
Abstract: No abstract text available
Text: SU5722845D8E6CL August 26, 2004 Ordering Information Part Numbers Description Module Speed SM5722845D8E6CL 128Mx72 1GB , DDR, 184-pin DIMM, Registered, ECC, 64Mx4 Based, DDR333B, 52.07mm, 22Ω DQ termination. PC2700 @ CL 2.5 SB5722845D8E6CL 128Mx72 (1GB), DDR, 184-pin DIMM, Registered, ECC,
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SU5722845D8E6CL
SM5722845D8E6CL
SB5722845D8E6CL
128Mx72
184-pin
64Mx4
DDR333B,
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PDF
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Untitled
Abstract: No abstract text available
Text: SM572168574E0BS August 22, 2001 Orderable Part Numbers Module Part Number SM572168574E0BS Description 16Mx72 128MB , SDRAM, 168-pin DIMM Registered, 16Mx8 Based, CL=2&3, PC133 Revision History • August 22, 2001 Datasheet released. Corporate Headquarters: P. O. Box 1757, Fremont, CA 94538, USA • Tel:(510) 623-1231 • Fax:(510) 623-1434 • E-mail: info@smartm.com
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Original
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SM572168574E0BS
16Mx72
128MB)
168-pin
16Mx8
PC133
128MByte
16Mx72)
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PDF
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SG572568
Abstract: No abstract text available
Text: SU5725685D8EBCU01 October 21, 2005 Ordering Information Part Numbers Description Module Speed SM5725685D8EBCL01 256Mx72 2GB , DDR, 184-pin DIMM, Registered, ECC, 128Mx8 Based (Stacked - two 128Mx4), DDR333B, 30.48mm, 22Ω DQ termination. PC2700 @ CL 2.5
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SU5725685D8EBCU01
SM5725685D8EBCL01
256Mx72
184-pin
128Mx8
128Mx4)
DDR333B,
SG572568
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PDF
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Untitled
Abstract: No abstract text available
Text: SU572284FD8E0CL01 Preliminary Ordering Information Part Numbers Description Module Speed SM572284FD8E0CL01 128Mx72 1GB , DDR, 184-pin DIMM, Registered, ECC, 128Mx4 Based, DDR333B, 18.29mm, 18Ω DQ termination. PC2700 @ CL 2.5 SB572284FD8E0CL01 128Mx72 (1GB), DDR, 184-pin DIMM, Registered, ECC,
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SU572284FD8E0CL01
SM572284FD8E0CL01
SB572284FD8E0CL01
128Mx72
184-pin
128Mx4
DDR333B,
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PDF
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Untitled
Abstract: No abstract text available
Text: SM5721685D4D0UU July 19, 2000 Revision History • July 19, 2000 Datasheet released. Corporate Headquarters: P. O. Box 1757, Fremont, CA 94538, USA • Tel: 510 623-1231 • Fax:(510) 623-1434 • E-mail: info@smartm.com Europe: 36 Linford Forum, Rockingham Dr., Linford Wood, Milton Keynes, MK14 6LY, UK • Tel: +44-1908 234030 • Fax: +44-1908-234191
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Original
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SM5721685D4D0UU
128MByte
16Mx8
184-pin
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PDF
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Untitled
Abstract: No abstract text available
Text: SM57204407UE6UU May 31, 2000 Revision History • May 31, 2000 Added Command Truth Table, Mode Register Table and notes. Modified waveforms Auto Refresh (CBR cycle and Power Down Mode and Clock Mask). • May 29, 1998 Datasheet released. Note* : A10/AP initiates Auto-precharge.
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SM57204407UE6UU
A10/AP
32MByte
72EREIN
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PDF
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Untitled
Abstract: No abstract text available
Text: SMART SM5720280UUDUGU Modular Technologies February 18, 1998 16MByte 2M x 72 DRAM Module - 2Mx8 based 168-pin DIMM, Non-buffered, ECC Features Part Numbers • • • • • • • • • • • SM57202800UDUGU SM57202801UDUGU SM57202808UDUGU SM57202809UDUGU
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SM5720280UUDUGU
16MByte
168-pin
SM57202800UDUGU
SM57202801UDUGU
SM57202808UDUGU
SM57202809UDUGU
50/60/70ns
300/400mil
AMP-390052-3
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PDF
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Untitled
Abstract: No abstract text available
Text: SM572088574D63R May 26, 2000 Revision History • May 26, 2000 Added Command Truth Table, Mode Register Table and notes. Modified waveforms Auto Refresh (CBR cycle and Power Down Mode and Clock Mask). • February 14, 2000 Modified module length from 133.37mm to 133.35mm.
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SM572088574D63R
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PDF
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SG572284578E83R
Abstract: SM572284578E83R
Text: SU572284578E83R January 2, 2007 Ordering Information Module Part Number Description SM572284578E83R 128Mx72 1GB , SDRAM, 168-pin DIMM, Registered, ECC, 128Mx4 Based (Stacked two 64Mx4), PC133, CL = 4.0 (Device = 3.0), 43.18mm. SG572284578E83R 128Mx72 (1GB), SDRAM, 168-pin DIMM, Registered, ECC, 128Mx4 Based (Stacked two 64Mx4), PC133, CL = 4.0 (Device = 3.0), 43.18mm, Green Module (RoHS Compliant).
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Original
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SU572284578E83R
SM572284578E83R
SG572284578E83R
128Mx72
168-pin
128Mx4
64Mx4)
PC133,
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PDF
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u351
Abstract: No abstract text available
Text: SU5725645D8E8CU August 27, 2004 Ordering Information Part Numbers Description Module Speed SM5725645D8E8CG 256Mx72 2GB , DDR, 184-pin DIMM, Registered, ECC, 128Mx4 (Stacked - two 64Mx4) Based, DDR266A, 52.07mm, 22Ω DQ termination. PC2100 @ CL 2.0, 2.5 SB5725645D8E8CG
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Original
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SU5725645D8E8CU
SM5725645D8E8CG
256Mx72
184-pin
128Mx4
64Mx4)
DDR266A,
u351
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PDF
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Untitled
Abstract: No abstract text available
Text: SM57202807UDWBU Preliminary Revision History • May 3, 2001 Modified datasheet. • May 10, 2000 Added Command Truth Table, Mode Register Table and notes. Modified waveforms Auto Refresh (CBR cycle and Power Down Mode and Clock Mask). • September 1, 1998
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SM57202807UDWBU
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PDF
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Untitled
Abstract: No abstract text available
Text: SU5722885D8D0CL July 20, 2006 Ordering Information Part Numbers Description Module Speed SM5722885D8D0CL 128Mx72 1GB , DDR, 184-pin DIMM, Unbuffered, ECC, 64Mx8 Based, DDR333B, 31.75mm, 22Ω DQ termination. PC2700 @ CL 2.5 SG5722885D8D0CL 128Mx72 (1GB), DDR, 184-pin DIMM, Unbuffered, ECC,
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Original
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SU5722885D8D0CL
SM5722885D8D0CL
SG5722885D8D0CL
128Mx72
184-pin
64Mx8
DDR333B,
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PDF
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Untitled
Abstract: No abstract text available
Text: SM57202807UD6UP May 25, 2000 Revision History • May 25, 2000 Added Command Truth Table, Mode Register Table and notes. Modified waveforms Auto Refresh (CBR cycle and Power Down Mode and Clock Mask). • January 6, 2000 Modified module length from 133.37mm to 133.35mm.
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Original
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SM57202807UD6UP
SM57202807UD6BP
SM57202807UD6UP.
44-1908-EREIN
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PDF
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Untitled
Abstract: No abstract text available
Text: SM572164U7UB6BU Preliminary D Revision History • June 17, 1999 Preliminary datasheet released. Corporate Headquarters: P. O. Box 1757, Fremont, CA 94538, USA • Tel: 510 623-1231 • Fax:(510) 623-1434 • E-mail: info@smartm.com Europe: 36 Linford Forum, Rockingham Dr., Linford Wood, Milton Keynes, MK14 6LY, UK • Tel: +44-1908 234030 • Fax: +44-1908-234191
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SM572164U7UB6BU
128MByte
16Mx4
200-pin
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PDF
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D56M42C5BH0M
Abstract: No abstract text available
Text: SU572124DD8E8CL February 3, 2006 Ordering Information Part Numbers Description Device Vendor SM572124DD8E8CL 512Mx72 4GB , DDR, 184-pin DIMM, Registered, ECC, 256Mx4 Based (Stacked - two 128Mx4), PC2700, DDR333B, 30.48mm, 18Ω DQ termination. Smart, Rev. 0
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SU572124DD8E8CL
SM572124DD8E8CL
512Mx72
184-pin
256Mx4
128Mx4)
PC2700,
DDR333B,
D56M42C5BH0M
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PDF
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Untitled
Abstract: No abstract text available
Text: SU5722885D8DRCU02 October 1, 2004 Ordering Information Part Numbers Description Module Speed SM5722885D8DRCG02 128Mx72 1GB , DDR, 200-pin SO-DIMM, Unbuffered, PLL, ECC, 128Mx8 Based (Stacked - two 64Mx8), DDR266A, 31.75mm, 22Ω DQ termination. PC2100 @ CL 2.0, 2.5
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SU5722885D8DRCU02
SM5722885D8DRCG02
128Mx72
200-pin
128Mx8
64Mx8)
DDR266A,
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PDF
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1773-ma
Abstract: SM572288FD8E0FN SU572288FD8E0FN
Text: SU572288FD8E0FN January 11, 2005 Ordering Information Part Numbers Description Module Speed SM572288FD8E0FN 128Mx72 1GB , DDR, 184-pin DIMM, Registered, ECC, 64Mx8 Based, DDR400C, 28.575mm, 22Ω DQ termination. PC3200 @ CL 3.0 SB572288FD8E0FN 128Mx72 (1GB), DDR, 184-pin DIMM, Registered, ECC,
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SU572288FD8E0FN
SM572288FD8E0FN
SB572288FD8E0FN
128Mx72
184-pin
64Mx8
DDR400C,
575mm,
1773-ma
SU572288FD8E0FN
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PDF
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Untitled
Abstract: No abstract text available
Text: SM572168574D0UP May 26, 2000 Revision History • April 14, 2000 Updated DC characteristics. Added Command Truth Table, Mode Register Table and notes. Modified waveforms Auto Refresh (CBR cycle and Power Down Mode and Clock Mask). • November 3, 1999 Corrected column addresses from A0~A8 to A0~A9 on page 3.
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SM572168574D0UP
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PDF
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Untitled
Abstract: No abstract text available
Text: SM572013001Q4GU August 1996 Rev 0 SMART Modular Technologies SM572013001Q4GU 8MByte 1M x 72 , 5.0V, CMOS DRAM Module - Buffered General Description Features The SM572013001Q4GU is a high performance, 8-megabyte dynamic RAM module organized as 1M words by 72 bits, in a 168-pin, dual-in-line (DIMM)
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SM572013001Q4GU
168-pin,
1Mx16
74ABT16244
74ACT11244)
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PDF
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Untitled
Abstract: No abstract text available
Text: SM572088574E6UP January 3, 2001 Revision History • January 3, 2001 Modified datasheet. • May 31, 2000 Added Command Truth Table, Mode Register Table and notes. Modified waveforms Auto Refresh (CBR cycle and Power Down Mode and Clock Mask). • March 9, 2000
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Original
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SM572088574E6UP
PC-100
SM572088574E6BP
SM572088574E6UP.
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PDF
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Untitled
Abstract: No abstract text available
Text: SU572284FD8E6CL January 11, 2005 Ordering Information Part Numbers Description Module Speed SM572284FD8E6CL 128Mx72 1GB , DDR, 184-pin DIMM, Registered, ECC, 64Mx4 Based, DDR333B, 30.48mm, 18Ω DQ termination. PC2700 @ CL 2.5 SB572284FD8E6CL 128Mx72 (1GB), DDR, 184-pin DIMM, Registered, ECC,
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Original
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SU572284FD8E6CL
SM572284FD8E6CL
SB572284FD8E6CL
128Mx72
184-pin
64Mx4
DDR333B,
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PDF
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SM579
Abstract: No abstract text available
Text: SM579 Rf - CL [Mohm] 1 Vdd= 5 FCR4.0M5 [V] Fig.a~d T a = 2 0 [deg] T y p i cal g a. V1H/V1L e. Duty [V] 400 300 200 100 70 60 [%] 54.2 50 ^43. 40 30 1 -20 f. Vstart m 20 CL1/CL2 40 60 80 [ pF ] Loading capacitance(CL1/CL2) dependence of oscillating characteristics (CL 1=CL2)
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OCR Scan
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SM579
SM579
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PDF
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