S3047
Abstract: U311D XS-3045
Text: PRELIMINARY DEVICE SPECIFICATION > 4 M C SO N E T/SD H O C -12 TO OC-48 MUX/DEIWUX FEATURES • Complies with ANSI, Bellcore and ITU-T specifications • Supports STS-12/STM-4 to STS-48/STM-16 Mux/Demux functions • 8-bit LVDS data path for STS-48/STM-16 data
|
OCR Scan
|
OC-48
S3045
STS-12/STM-4
STS-48/STM-16
S3041/S3042
PM5355
PM5312
311CLKINP
S3047
U311D
XS-3045
|
PDF
|
st7011
Abstract: st6129 P15L100 valor st7011 VALOR lan transformer network interface card 802.3 circuit diagram st7011 valor pulse TRANSFORMER valor st7011 transformer Twisted Pair split termination
Text: May 1996 Application Note 56 ML6692 and DEC 21142 Adapter Implementation OVERVIEW This Application Note describes the design of a 10/100 Network Interface Card NIC with auto-negotiation utilizing the DEC 21142 Media Access Controller (MAC) and the ML6692 100BASE-TX Physical Layer (PHY) from
|
Original
|
ML6692
100BASE-TX
10BASE-T
st7011
st6129
P15L100
valor st7011
VALOR lan transformer
network interface card 802.3 circuit diagram
st7011 valor
pulse TRANSFORMER valor
st7011 transformer
Twisted Pair split termination
|
PDF
|
2161B
Abstract: No abstract text available
Text: APPLICATION NOTE H8S/2100 Series I2C Communication Using a Repeated Start Condition Master Transmit/Receive Operation Introduction The H8S/2114 (master device) transmits 1-byte data to a slave device by means of channel 0 of the I2C bus interface. After transmitting the 1-byte data, the master device generates a repeated start condition and receives 128-byte data
|
Original
|
H8S/2100
H8S/2114
128-byte
H8S/2104
H8S/2111B
H8S/2110B
H8S/2140B
H8S/2141B
H8S/2160B
2161B
|
PDF
|
Untitled
Abstract: No abstract text available
Text: APPLICATION NOTE H8S/2100 Series I2C Master Receive Mode 1 byte Introduction The H8S/2114 receives 1-byte data from a slave device by means of channel 0 of the I2C bus interface. The frequency of the transfer clock is 100 kHz. Target Device H8S/2114 H8S/2104
|
Original
|
H8S/2100
H8S/2114
H8S/2114
H8S/2104
H8S/2111B
H8S/2110B
H8S/2140B
H8S/2141B
H8S/2160B
H8S/2161B
|
PDF
|
A6583
Abstract: a6581 A6562 CRC-16 and CRC-32 CRC-16 and CRC-32 Ethernet a6585 Cat3 Cable protocol contact id sia i/o protocol contact id sia manchester encoder
Text: 21145 Phoneline/Ethernet LAN Controller Hardware Reference Manual April 1999 Order Number: 278211-001 Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual
|
Original
|
10-MHz
100BASE-FX
100BASE-T
100BASE-TX
100BASE-T4
100BASE-X
A6583
a6581
A6562
CRC-16 and CRC-32
CRC-16 and CRC-32 Ethernet
a6585
Cat3 Cable
protocol contact id sia i/o
protocol contact id sia
manchester encoder
|
PDF
|
Untitled
Abstract: No abstract text available
Text: APPLICATION NOTE H8S/2100 Series I2C Master Transmit Mode 128 bytes Introduction The H8S/2114 transmits 128 bytes of data to a slave device by means of channel 0 of the I2C bus interface. The frequency of the transfer clock is 100 kHz. Target Device H8S/2114
|
Original
|
H8S/2100
H8S/2114
H8S/2114
H8S/2104
H8S/2111B
H8S/2110B
H8S/2140B
H8S/2141B
H8S/2160B
H8S/2161B
|
PDF
|
Untitled
Abstract: No abstract text available
Text: APPLICATION NOTE H8S/2100 Series Interrupt Handling during I2C Communication master receive operation Introduction The H8S/2114 receives 128 bytes of data from a slave device by means of channel 0 of the I2C bus interface. During the communication, interrupts are generated using a free-running timer. The frequency of the transfer clock is 100 kHz.
|
Original
|
H8S/2100
H8S/2114
H8S/2114
H8S/2104
H8S/2111B
H8S/2110B
H8S/2140B
H8S/2141B
H8S/2160B
H8S/2161B
|
PDF
|
Untitled
Abstract: No abstract text available
Text: APPLICATION NOTE H8S/2100 Series I2C Master Receive Mode 128 bytes Introduction The H8S/2114 receives 128 bytes of data from a slave device by means of channel 0 of the I2C bus interface. The frequency of the transfer clock is 100 kHz. Target Device H8S/2114
|
Original
|
H8S/2100
H8S/2114
H8S/2114
H8S/2104
H8S/2111B
H8S/2110B
H8S/2140B
H8S/2141B
H8S/2160B
H8S/2161B
|
PDF
|
Untitled
Abstract: No abstract text available
Text: APPLICATION NOTE H8S/2100 Series I2C Master Transmit Mode 1 byte Introduction The H8S/2114 transmits 1-byte data to a slave device by means of channel 0 of the I2C bus interface. The frequency of the transfer clock is 100 kHz. Target Device H8S/2114 H8S/2104
|
Original
|
H8S/2100
H8S/2114
H8S/2114
H8S/2104
H8S/2111B
H8S/2110B
H8S/2140B
H8S/2141B
H8S/2160B
H8S/2161B
|
PDF
|
ASJ CR21
Abstract: Diode GEP 53A 93c46m8 D1275 ASJ PTE CR21 ASJ em 483 epson 93c46-m8 Diode GEP 23A D12301
Text: June 1997 Application Note 65 ML6698 and DEC 21143 Adapter Implementation OVERVIEW The interface between the DEC 21143 and the ML6698 is a mix of digital and analog signals. The DEC 21143’s 5-bit interface connects to the ML6698’s 5-bit interface for 100BASE-TX operation. The ML6698 100BASE-TX
|
Original
|
ML6698
100BASE-TX
100BASE-TX
ASJ CR21
Diode GEP 53A
93c46m8
D1275
ASJ PTE
CR21 ASJ
em 483 epson
93c46-m8
Diode GEP 23A
D12301
|
PDF
|
Am91L24
Abstract: 2114 static ram memory 2114L 91l24 memory ic 2114 pin out ram 2114L 2114L RAM 91L14 2114 1k x 16 RAM 4096N
Text: IMPROVED PERFORMANCE WITH THE Am9124 By Alex Shevekov, Paul Liu and Joe Kroeger INTRODUCTION off the top of the chart with a value of about .28mW/bit. Note that the Am91L02C, 2114, 2114L, Am9114C, and Am91L14C are straight lines; their dissipation does not depend on the state of
|
OCR Scan
|
Am9124
Am9124
4096-bit
18-pin
Am9114,
Am9124.
MOS-370
Am91L24
2114 static ram memory
2114L
91l24
memory ic 2114 pin out
ram 2114L
2114L RAM
91L14
2114 1k x 16 RAM
4096N
|
PDF
|
lpc1768 gpio
Abstract: No abstract text available
Text: UM10493 POS Reference Design - Firmware description Rev. 1.2 — 4 October 2012 211412 User manual COMPANY PUBLIC Document information Info Content Keywords PN512, TDA8026, LPC1768, Point of sales terminal, Reference Design Abstract This user manual presents the NXP POS_RD evaluation board. This
|
Original
|
UM10493
PN512,
TDA8026,
LPC1768,
LPC1768:
lpc1768 gpio
|
PDF
|
1N14B
Abstract: CISTPL_BAR 100PF 28F020 29F010 74FCT823 74HCT374 DC21143 HCT132 BATTERY CIS
Text: Digital Semiconductor 21142 and 21143 CardBus Implementation Guidelines: An Application Note Order Number: EC-QZ1XA-TE November 1996 This document provides design guidelines for CardBus implementation using the Digital Semiconductor 21142 and 21143 Fast Ethernet LAN controllers.
|
Original
|
|
PDF
|
Untitled
Abstract: No abstract text available
Text: APPLICATION NOTE H8S/2100 Series I2C Slave Transmit Mode 1 byte Introduction By means of channel 0 of the I2C bus interface, the H8S/2114 transmits 1-byte data to the master device in slave transmit mode. The frequency of the transfer clock is 100 kHz. Target Device
|
Original
|
H8S/2100
H8S/2114
H8S/2114
H8S/2104
H8S/2111B
H8S/2110B
H8S/2140B
H8S/2141B
H8S/2160B
H8S/2161B
|
PDF
|
|
|
1N14B
Abstract: HCT132 100PF 28F020 29F010 74FCT823 74HCT374 DC21143 idh 34 pin connector Image CIS
Text: Digital Semiconductor 21142 and 21143 CardBus Implementation Guidelines: An Application Note Order Number: EC-QZ1XA-TE November 1996 This document provides design guidelines for CardBus implementation using the Digital Semiconductor 21142 and 21143 Fast Ethernet LAN controllers.
|
Original
|
|
PDF
|
Untitled
Abstract: No abstract text available
Text: APPLICATION NOTE H8S/2100 Series I2C Slave Transmit Mode 128 bytes Introduction By means of channel 0 of the I2C bus interface, the H8S/2114 transmits 128-byte data to the master device in slave transmit mode. The frequency of the transfer clock is 100 kHz.
|
Original
|
H8S/2100
H8S/2114
128-byte
H8S/2114
H8S/2104
H8S/2111B
H8S/2110B
H8S/2140B
H8S/2141B
H8S/2160B
|
PDF
|
SN76477
Abstract: TNY 176 PN EQUIVALENT 2n4401 free transistor equivalent book tis43 XR2206 application notes Semiconductor Data Handbook mj802 2N3866 s2p bc149c TIP35C TIP36C sub amplifier circuit diagram LM131
Text: From the Publishers of ETI & HE HEM M iNqs E U c t r o n ic s L rd Electronic C om ponents Et M icrocom puters 16 BRAND STREET, HITCHIN, HERTS, SG5 1JE Telephone: 0462 33031 memories 2114L 2708 2716 2532 2732 4116 4164 6116P3 6116LP3 •Op 220p 210p 380p
|
OCR Scan
|
2114L
6116P3
6116LP3
AY-3-1270
AY-3-1350
AY-3-8910
AY-3-8912
AY-5-1230
CA3080E
CA3130E
SN76477
TNY 176 PN EQUIVALENT
2n4401 free transistor equivalent book
tis43
XR2206 application notes
Semiconductor Data Handbook mj802
2N3866 s2p
bc149c
TIP35C TIP36C sub amplifier circuit diagram
LM131
|
PDF
|
Untitled
Abstract: No abstract text available
Text: ¿ = 7 S G S -T H O M S O N T E A 2114 VIDEO SWITCH • 2 V ID E O O U T P U T S W IT H 1 5 0 ß LO A D D R IV E C A P A B ILIT Y ■ D Y N A M IC O U T P U T A M P L IT U D E 4 V p p ON EACH O U TP U T ■ B A N D W ID T H 1 8 M H z T Y P ■ C L A M P E D V ID E O IN P U T S
|
OCR Scan
|
TEA2114
|
PDF
|
Untitled
Abstract: No abstract text available
Text: APPLICATION NOTE H8S/2100 Series I2C Slave Receive Mode 1 byte Introduction By means of channel 0 of the I2C bus interface, the H8S/2114 receives 1-byte data from the master device in slave receive mode. The frequency of the transfer clock is 100 kHz. Target Device
|
Original
|
H8S/2100
H8S/2114
H8S/2114
H8S/2104
H8S/2111B
H8S/2110B
H8S/2140B
H8S/2141B
H8S/2160B
H8S/2161B
|
PDF
|
Untitled
Abstract: No abstract text available
Text: APPLICATION NOTE H8S/2100 Series I2C Slave Receive Mode 128 bytes Introduction By means of channel 0 of the I2C bus interface, the H8S/2114 receives 128-byte data from the master device in slave receive mode. The frequency of the transfer clock is 100 kHz.
|
Original
|
H8S/2100
H8S/2114
128-byte
H8S/2114
H8S/2104
H8S/2111B
H8S/2110B
H8S/2140B
H8S/2141B
H8S/2160B
|
PDF
|
2114 Ram pinout 18
Abstract: No abstract text available
Text: MWS5114 H A R R IS S E M I C O N D U C T O R 1024-Word x 4-Bit LSI Static RAM February 1992 Description Features • Fully Static Operation • Industry Standard 1024 x 4 Pinout Same as Pinouts for 6514, 2114, 9114, and 404S Types • Common Data Input and Output
|
OCR Scan
|
MWS5114
1024-Word
MWS5114
MWS5114-3
MWS5114-2
MWS5114-1
2114 Ram pinout 18
|
PDF
|
Untitled
Abstract: No abstract text available
Text: Random-Access Memories RAMs MWS5114 a6 — I I8 “ VDD A5 — 2 I7 — A? * 4 - 3 I6 a 3 — 4 I - «8 I5 - A g CMOS 1024-Word by 4-Bit LSI Static RAM Ao — 5 I4 — I/O t Features: A| — 6 I3 — 1 / 0 2 7 I2 - I / O 3 • Fully static operation ■ In d u s try s ta n d a rd 1024 x 4 p in o u t (sam e as p in o u ts fo r 6514, 2114,
|
OCR Scan
|
MWS5114
1024-Word
30982R
92CS-3III4R2
|
PDF
|
VDR 20-100
Abstract: MWS5114 MWS5114D1 MWS5114D2 MWS5114D3 MWS5114D3X MWS5114E1 MWS5114E2 MWS5114E2X MWS5114E3
Text: MWS5114 TM 1024-Word x 4-Bit LSI Static RAM March 1997 Features as 2V Min • Fully Static Operation • All Inputs and Outputs Directly TTL Compatible • Industry Standard 1024 x 4 Pinout Same as Pinouts for 6514, 2114, 9114, and 4045 Types • Three-State Outputs
|
Original
|
MWS5114
1024-Word
200ns
250ns
300ns
MWS5114E3
MWS5114E2
MWS5114E2X
MWS5114E1
MWS5114D3
VDR 20-100
MWS5114
MWS5114D1
MWS5114D2
MWS5114D3
MWS5114D3X
MWS5114E1
MWS5114E2
MWS5114E2X
MWS5114E3
|
PDF
|
R2114P
Abstract: R2114
Text: PART NUMBER DOCUM ENT NO. 2 9 0 0 0 D 44 REVISION 2. OCT. 1 97 8 * Rockwell R 2114 R 6500 Microcomputer System DATA SHEET 1024 X 4 STATIC RANDOM ACCESS M EMORY R2114 SYSTEM ABSTRACT FEATURES T h e ' 8 -b it R 6 50 0 m icro co m p u te r system is produced w ith N-
|
OCR Scan
|
R2114
R2114P
R2114
|
PDF
|
